Abstract: The present invention relates to a thin film transistor array panel and a display device including the same. A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a plurality of gate lines; a plurality of pixels respectively connected to the gate lines; a gate driver comprising a plurality of stages connected to each other, the plurality of stages being respectively connected to the plurality of gate lines and applying gate signals to the plurality of gate lines; and a driver inspection unit separated from the gate driver and including at least three inspection stages, wherein each of the at least three inspection stages has a same structure as one of the plurality of stages of the gate driver.

Abstract: A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material.

Abstract: A color filter substrate includes a transparent substrate, a light-blocking layer, a color filter layer, a first cell gap maintaining member and a second cell gap maintaining member. The transparent substrate has a plurality of pixel regions. Each of the pixel regions includes first and second regions. The light-blocking layer is disposed over the transparent substrate. The light-blocking layer blocks light that leaks through boundaries of the pixel regions. The color filter layer is disposed over the transparent substrate. The color filter layer has a first thickness at the first region and a second thickness that is smaller than the first thickness at the second region. The first cell gap maintaining member is disposed at the first region. The second cell gap maintaining member is disposed at the second region. Therefore, a height difference between the main column spacer and the sub column spacer may be easily adjusted.

Abstract: A liquid crystal display (LCD) having high luminance and color renditions is provided. The liquid crystal display includes a first insulating substrate, a gate line and a data line crossing each other on the first insulating substrate to define a pixel. First and second sub-pixel electrodes divide the pixel into two parts. A first switching element drives the first sub-pixel electrode and a second switching element drives the second sub-pixel electrode. A second insulating substrate faces the first insulating substrate. A color pattern is arranged on the second insulating substrate and overlaps the first sub-pixel electrode. A contrast pattern overlaps the second sub-pixel electrode.

Abstract: In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes.

Abstract: A liquid crystal display includes a conductive spacer that connects a common voltage line of an array substrate to a common electrode of an opposite substrate. The conductive spacer has a bar-like shape and extends along the common voltage line.

Abstract: A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

Abstract: The present invention relates to a thin film transistor array panel and a display device including the same. A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a plurality of gate lines; a plurality of pixels respectively connected to the gate lines; a gate driver comprising a plurality of stages connected to each other, the plurality of stages being respectively connected to the plurality of gate lines and applying gate signals to the plurality of gate lines; and a driver inspection unit separated from the gate driver and including at least three inspection stages, wherein each of the at least three inspection stages has a same structure as one of the plurality of stages of the gate driver.

Abstract: A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

Abstract: A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material.

Abstract: In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes.

Abstract: A liquid crystal display (LCD) having high luminance and color renditions is provided. The liquid crystal display includes a first insulating substrate, a gate line and a data line crossing each other on the first insulating substrate to define a pixel. First and second sub-pixel electrodes divide the pixel into two parts. A first switching element drives the first sub-pixel electrode and a second switching element drives the second sub-pixel electrode. A second insulating substrate faces the first insulating substrate. A color pattern is arranged on the second insulating substrate and overlaps the first sub-pixel electrode. A contrast pattern overlaps the second sub-pixel electrode.

Abstract: A liquid crystal display includes a conductive spacer that connects a common voltage line of an array substrate to a common electrode of an opposite substrate. The conductive spacer has a bar-like shape and extends along the common voltage line.