Patents by Inventor Bae-Seong Kwon
Bae-Seong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240349621Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Inventors: Yongjae Kim, Kuhoon Chung, Gwanhyeob Koh, Bae-Seong Kwon, Kyungtae Nam
-
Patent number: 12058941Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.Type: GrantFiled: October 29, 2020Date of Patent: August 6, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yongjae Kim, Kuhoon Chung, Gwanhyeob Koh, Bae-Seong Kwon, Kyungtae Nam
-
Patent number: 11152561Abstract: A magnetic memory device includes a lower contact plug on a substrate, a magnetic tunnel junction pattern on the lower contact plug, a bottom electrode, which is between the lower contact plug and the magnetic tunnel junction pattern and is in contact with a bottom surface of the magnetic tunnel junction pattern, and a top electrode on a top surface of the magnetic tunnel junction pattern. Each of the bottom electrode, the magnetic tunnel junction pattern, and the top electrode has a thickness in a first direction, which is perpendicular to a top surface of the substrate. A first thickness of the bottom electrode is about 0.6 to 1.1 times a second thickness of the magnetic tunnel junction pattern.Type: GrantFiled: May 5, 2020Date of Patent: October 19, 2021Inventors: Bae-Seong Kwon, Yongjae Kim, Kyungtae Nam, Kuhoon Chung
-
Publication number: 20210242396Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.Type: ApplicationFiled: October 29, 2020Publication date: August 5, 2021Inventors: Yongjae Kim, Kuhoon Chung, Gwanhyeob Koh, Bae-Seong Kwon, Kyungtae Nam
-
Publication number: 20200395531Abstract: A magnetic memory device includes a lower contact plug on a substrate, a magnetic tunnel junction pattern on the lower contact plug, a bottom electrode, which is between the lower contact plug and the magnetic tunnel junction pattern and is in contact with a bottom surface of the magnetic tunnel junction pattern, and a top electrode on a top surface of the magnetic tunnel junction pattern. Each of the bottom electrode, the magnetic tunnel junction pattern, and the top electrode has a thickness in a first direction, which is perpendicular to a top surface of the substrate. A first thickness of the bottom electrode is about 0.6 to 1.1 times a second thickness of the magnetic tunnel junction pattern.Type: ApplicationFiled: May 5, 2020Publication date: December 17, 2020Inventors: Bae-Seong Kwon, Yongjae Kim, Kyungtae Nam, Kuhoon Chung
-
Patent number: 9312184Abstract: In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.Type: GrantFiled: March 7, 2014Date of Patent: April 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tea-Kwang Yu, Bae-Seong Kwon, Yong-Tae Kim, Chul-Ho Chung, Yong-Suk Choi
-
Publication number: 20140264538Abstract: In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.Type: ApplicationFiled: March 7, 2014Publication date: September 18, 2014Inventors: Tea-Kwang YU, Bae-Seong KWON, Yong-Tae KIM, Chul-Ho CHUNG, Yong-Suk CHOI
-
Patent number: 7855410Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.Type: GrantFiled: July 7, 2008Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Suk Choi, Hyok-Ki Kwon, Bae-Seong Kwon
-
Publication number: 20100103744Abstract: A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors.Type: ApplicationFiled: October 23, 2009Publication date: April 29, 2010Inventors: Seung-jin Yang, Jeong-uk Han, Yong-tae Kim, Yong-suk Choi, Bae-seong Kwon
-
Publication number: 20100001328Abstract: A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer.Type: ApplicationFiled: July 7, 2009Publication date: January 7, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Tae Kim, Yong-Suk Choi, Bae-Seong Kwon
-
Publication number: 20090008696Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.Type: ApplicationFiled: July 7, 2008Publication date: January 8, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jin YANG, Jeong-Uk HAN, Yong-Suk CHOI, Hyok-Ki KWON, Bae-Seong KWON