Abstract: A cache memory uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. In a semi-associative instruction cache, with the CAM and eight cache lines grouped together to form camlets, a binary index is used to address one camlet in the cache array, and the effective address tag match is used to select a potential line within the camlet in accessing data stored in the cache array. Since an E-tag match causes that cache line's wordline to activate, proper cache operation requires that no two (or more) E-tags within a camlet have the same match criteria (ECAM entry); the invalidation of entries is done to prevent this from happening. Due to the mapping of the effective address into the E-tag CAM and the camlet binary index, addresses that are 1-Meg apart point to the same camlet and have the same ECAM tag. The method thus employs a semi-associative cache having cache lines configured in camlets of, for example, eight lines per camlet.