Patents by Inventor Bahattin Kilic

Bahattin Kilic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM
    Publication number: 20240039539
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Systems and methods for implementing a scalable system
    Patent number: 11831312
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: November 28, 2023
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM
    Publication number: 20220231687
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: February 23, 2022
    Publication date: July 21, 2022
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Systems and methods for implementing a scalable system
    Patent number: 11309895
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM
    Publication number: 20200389172
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 10, 2020
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Systems and methods for implementing a scalable system
    Patent number: 10742217
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 11, 2020
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM
    Publication number: 20190319626
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: February 4, 2019
    Publication date: October 17, 2019
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu