Patents by Inventor Baheerathan Anandharengan

Baheerathan Anandharengan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230345021
    Abstract: A system for storing and retrieving data for a multi-stage two-dimensional transform is disclosed. The system comprises a memory comprising storage elements arranged in a physical grid with physical rows and physical columns, wherein values stored in a same physical column are not simultaneously accessible. A processing unit is configured to receive data elements of a certain logical row of a dataset arranged in logical rows and logical columns for storage in a certain physical row of the physical grid of the memory. The processing unit is configured to circularly shift the data elements based on a shift offset associated with the certain physical row. The processing unit is configured to provide for storage in the certain physical row of the physical grid of the memory the circularly shifted data elements to enable a logical column of the dataset to be read together from different physical columns.
    Type: Application
    Filed: November 12, 2021
    Publication date: October 26, 2023
    Inventors: Zhao Wang, Yunqing Chen, Baheerathan Anandharengan
  • Patent number: 11683498
    Abstract: A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 20, 2023
    Assignee: Meta Platforms, Inc.
    Inventors: Zhao Wang, Srikanth Alaparthi, Yunqing Chen, Baheerathan Anandharengan, Gaurang Chaudhari, Junqiang Lan, Harikrishna Madadi Reddy, Prahlad Rao Venkatapuram
  • Patent number: 11606568
    Abstract: A video encoder comprises an application-specific integrated circuit (ASIC) video encoding unit configured to receive via an interface in a processing order, quantized transform coefficients for a transform unit of a frame of a video being encoded. The ASIC unit is configured to analyze at least a portion of the quantized transform coefficients in the processing order to identify one or more end-of-block candidate positions in the processing order. The ASIC unit is configured to translate the one or more end-of-block candidate positions for the at least a portion of the quantized transform coefficients to one or more scan order versions of the one or more end-of-block candidate positions. The ASIC unit is configured to determine a true end-of-block position for the quantized transform coefficients using the one or more scan order versions of the one or more end-of-block candidate positions.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: March 14, 2023
    Assignee: Meta Platforms, Inc.
    Inventors: Zhao Wang, Yunqing Chen, Baheerathan Anandharengan
  • Publication number: 20230048150
    Abstract: A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: January 28, 2022
    Publication date: February 16, 2023
    Inventors: Zhao Wang, Srikanth Alaparthi, Yunqing Chen, Baheerathan Anandharengan, Gaurang Chaudhari, Junqiang Lan, Harikrishna Madadi Reddy, Prahlad Rao Venkatapuram
  • Publication number: 20230052538
    Abstract: A disclosed method may include storing, within a hardware memory device included as part of a rate—distortion optimization (RDO) hardware pipeline, at least one transform unit table that (1) is pregenerated from a seed probability table for transformation of video data in accordance with a video encoding standard, (2) corresponds to a transform operation supported by the video encoding standard, and (3) corresponds to a transform unit included in the RDO hardware pipeline. The method may also include determining, by accessing the transform unit table, an RDO token rate for an encoding of the video data by a hardware video encoding pipeline that includes the RDO hardware pipeline, and selecting, based on the RDO token rate, a transform operation for the encoding of the video data.
    Type: Application
    Filed: January 28, 2022
    Publication date: February 16, 2023
    Inventors: Zhao Wang, Srikanth Alaparthi, Yunqing Chen, Baheerathan Anandharengan, Gaurang Chaudhari, Junqiang Lan, Harikrishna Madadi Reddy, Prahlad Rao Venkatapuram
  • Patent number: 11425393
    Abstract: A system for calculating token rates for video encoding includes a plurality of different probability lookup tables implemented in hardware, wherein each of the probability lookup tables specifically corresponds to a different prediction mode of a video codec. The system includes an application-specific integrated circuit compute unit. For each candidate prediction mode among the different prediction modes, the application-specific integrated circuit is configured to determine a rate distortion cost (RD Cost) for a video. The application-specific integrated circuit is configured to select one of the plurality of different probability lookup tables that corresponds to the candidate prediction mode and use the selected one of the plurality of different probability lookup tables to calculate a corresponding token rate for the candidate prediction mode.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: August 23, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Zhao Wang, Srikanth Alaparthi, Yunqing Chen, Baheerathan Anandharengan, Gaurang Chaudhari, Junqiang Lan, Harikrishna Madadi Reddy, Prahlad Rao Venkatapuram
  • Publication number: 20210319130
    Abstract: The disclosed may include various systems and methods for improving the efficiency and scalability of large-scale systems. For example, the disclosed may include systems and methods for automatic privacy enforcement using privacy-aware infrastructure, scalable general-purpose low cost integer motion search, efficient scaler filter coefficients layout for flexible scaling quality control with limited hardware resources, hardware optimization for power saving with both different codecs enabled, optimizing storage overhead and performance for large distributed data warehouse, mass and volume efficient integration of intersatellite link terminals to a satellite bus, and overcoming retention limit for memory-based distributed database systems.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 14, 2021
    Inventors: Yi Huang, Wenlong Dong, Marc Alexander Celani, Xianliang Zha, Yunqing Chen, Harikrishna Madadi Reddy, Junqiang Lan, Chien Cheng Liu, Raghuvardhan Moola, Haluk Ucar, Sujith Srinivasan, Handong Li, Xing Cindy Chen, Tuo Wang, Zhao Wang, Baheerathan Anandharengan, Gaurang Chaudhari, Prahlad Rao Venkatapuram, Srikanth Alaparthi, James Alexander Morle, Vincent Matthew Malfa, Yassir Azziz, Chien-Chung Chen, Yan Cui, Pedro Eugenio Rocha Pedreira, Stavros Harizopoulos