Abstract: Three-dimensional application specific integrated circuit (IC) architecture is described herein. In one aspect, an IC may include a first die including: a first semiconductor layer; a plurality of processing elements (PEs) located on the first semiconductor layer; and a first interface region of the first semiconductor layer, electrically coupled to the plurality of PEs and configured to communicate electrical signals with the plurality of PEs; a second die including: a second semiconductor layer; a plurality of IC elements located on the second semiconductor layer; and a second interface region of the second semiconductor layer, electrically coupled to the plurality of IC elements and configured to communicate electrical signals to the plurality of IC elements, where the first interface region and the second interface region are electrically coupled to each other and configured to transmit electrical signals between the plurality of PEs and the plurality of IC elements.

Abstract: In some embodiments, a system-on-chip, includes a central processing unit (CPU); an accelerator coupled to the CPU via a first die-to-die interconnect; and uniform memory coupled to the CPU via a second die-to-die interconnect. In some embodiments, in order to prevent use of accelerator memory for processing operations by the accelerator, the accelerator utilizes a uniform memory access tunneling system located in the accelerator to tunnel a high-level interconnect protocol associated with the second die-to-die interconnect to a die-to-die interconnect protocol associated with the first die-to-die interconnect, the uniform memory access tunneling system being configured to allow access to the uniform memory using a shared address space.

Abstract: In some embodiments, a method includes receiving, at a central processing unit (CPU)-based demultiplexer of a CPU, an input video data stream; performing, at the CPU, an accelerator decoding configuration assessment of an accelerator decoding configuration of an accelerator; and based upon the accelerator decoding configuration assessment, dynamically decoding CPU-based demultiplexer output from the CPU-based demultiplexer using a CPU-based decoding unit and an accelerator-based decoding unit. In some embodiments of the method, the accelerator decoding configuration assessment includes performing an accelerator-based decoding unit hardware configuration assessment of the accelerator-based decoding unit and a CPU-based decoding unit software configuration assessment of the CPU-based decoding unit software utilized for the CPU-based decoding unit.

Abstract: In some embodiments, a computer-implemented method includes receiving, at a security agent of a host central processing unit (CPU), accelerator firmware from flash memory; determining, at the security agent, whether the accelerator firmware includes a critical accelerator firmware component or a non-critical accelerator firmware component; authenticating, at the security agent, the critical accelerator firmware component instantaneously upon a determination that the accelerator firmware is the critical accelerator firmware component, wherein authenticating the critical accelerator firmware component yields an authenticated critical accelerator firmware component; and providing the authenticated critical accelerator firmware component to an accelerator via a sideband bus for execution at the accelerator.

Abstract: A system for storing and retrieving data for a multi-stage two-dimensional transform is disclosed. The system comprises a memory comprising storage elements arranged in a physical grid with physical rows and physical columns, wherein values stored in a same physical column are not simultaneously accessible. A processing unit is configured to receive data elements of a certain logical row of a dataset arranged in logical rows and logical columns for storage in a certain physical row of the physical grid of the memory. The processing unit is configured to circularly shift the data elements based on a shift offset associated with the certain physical row. The processing unit is configured to provide for storage in the certain physical row of the physical grid of the memory the circularly shifted data elements to enable a logical column of the dataset to be read together from different physical columns.

Abstract: A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A video encoder comprises an application-specific integrated circuit (ASIC) video encoding unit configured to receive via an interface in a processing order, quantized transform coefficients for a transform unit of a frame of a video being encoded. The ASIC unit is configured to analyze at least a portion of the quantized transform coefficients in the processing order to identify one or more end-of-block candidate positions in the processing order. The ASIC unit is configured to translate the one or more end-of-block candidate positions for the at least a portion of the quantized transform coefficients to one or more scan order versions of the one or more end-of-block candidate positions. The ASIC unit is configured to determine a true end-of-block position for the quantized transform coefficients using the one or more scan order versions of the one or more end-of-block candidate positions.

Abstract: A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A disclosed method may include storing, within a hardware memory device included as part of a rate—distortion optimization (RDO) hardware pipeline, at least one transform unit table that (1) is pregenerated from a seed probability table for transformation of video data in accordance with a video encoding standard, (2) corresponds to a transform operation supported by the video encoding standard, and (3) corresponds to a transform unit included in the RDO hardware pipeline. The method may also include determining, by accessing the transform unit table, an RDO token rate for an encoding of the video data by a hardware video encoding pipeline that includes the RDO hardware pipeline, and selecting, based on the RDO token rate, a transform operation for the encoding of the video data.

Abstract: A system for calculating token rates for video encoding includes a plurality of different probability lookup tables implemented in hardware, wherein each of the probability lookup tables specifically corresponds to a different prediction mode of a video codec. The system includes an application-specific integrated circuit compute unit. For each candidate prediction mode among the different prediction modes, the application-specific integrated circuit is configured to determine a rate distortion cost (RD Cost) for a video. The application-specific integrated circuit is configured to select one of the plurality of different probability lookup tables that corresponds to the candidate prediction mode and use the selected one of the plurality of different probability lookup tables to calculate a corresponding token rate for the candidate prediction mode.

Abstract: The disclosed may include various systems and methods for improving the efficiency and scalability of large-scale systems. For example, the disclosed may include systems and methods for automatic privacy enforcement using privacy-aware infrastructure, scalable general-purpose low cost integer motion search, efficient scaler filter coefficients layout for flexible scaling quality control with limited hardware resources, hardware optimization for power saving with both different codecs enabled, optimizing storage overhead and performance for large distributed data warehouse, mass and volume efficient integration of intersatellite link terminals to a satellite bus, and overcoming retention limit for memory-based distributed database systems.