Abstract: An apparatus having first, second and third processors of a multi-core processor is disclosed. The first processor is configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream. The second processor (i) operates as a slave to the first processor and (ii) is configured to perform one or more second operations in the decoding of the macroblocks. The third processor (i) operates as a slave to the second processor and (ii) is configured to perform one or more third operations in the decoding of the macroblocks.

Abstract: The invention relates to a method of concealing errors attributed to missing frames in a Motion Picture Expert Group-2 video stream, including the steps of: receiving a new frame for decoding and a “frame missing” flag that is set to a value associated with the occurrence of a missing frame, parsing the new frame to recover a picture type and a frame structure of the new frame, retrieving a picture type and a frame structure of a previous frame decoded immediately prior to the new frame, assigning a picture type and a frame structure to the missing frame based on the picture type and frame-structure values of the previous frame and the new frame and then applying an error concealment technique based upon the assigned picture type and frame structure of the missing frame.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: An apparatus having first, second and third processors of a multi-core processor is disclosed. The first processor is configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream. The second processor (i) operates as a slave to the first processor and (ii) is configured to perform one or more second operations in the decoding of the macroblocks. The third processor (i) operates as a slave to the second processor and (ii) is configured to perform one or more third operations in the decoding of the macroblocks.

Abstract: An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Abstract: The invention relates to a method of concealing errors attributed to missing frames in a Motion Picture Expert Group-2 video stream, including the steps of: receiving a new frame for decoding and a “frame missing” flag that is set to a value associated with the occurrence of a missing frame, parsing the new frame to recover a picture type and a frame structure of the new frame, retrieving a picture type and a frame structure of a previous frame decoded immediately prior to the new frame, assigning a picture type and a frame structure to the missing frame based on the picture type and frame-structure values of the previous frame and the new frame and then applying an error concealment technique based upon the assigned picture type and frame structure of the missing frame.

Abstract: A method of concealing errors in picture header information within H.263-encoded video compares current group-of-block frame identification (GFID) information to GFID information from the previous frame. If the GFID values are equal, the picture header information from the previous frame is used to decode the current frame. Otherwise, a selected parameter in the previous picture header information (for example, “picture type”) is altered and decoding proceeds with the altered picture header information. Preferably, only a portion of the current frame is initially decoded and validated prior to decoding the remainder of the frame. If the decoded portion is error-free, the decoding continues with the selected picture header information. If errors are found in the decoded portion, the picture header information is modified and the decoding process continues accordingly.

Abstract: A unique real time tuning (RTT) process is employed for obtaining the desired optimum device parameter adjustments. The RTT parameter adjustment process is utilized with IP phone or other device chipsets as desired. In one embodiment, RTT provides a graphical user interface to a digital signal processor (DSP), or the like, on the device chipset allowing for observation, evaluation and control of the device parameters in real time. The real time exchange of the device parameter information between the device and an external workstation, e.g., a personal computer or the like, is provided by a User Datagram Protocol (UDP) that runs on a controller on the device, e.g., an ARM processor or the like. In this example, the unique combination of the RTT, UDP and DSP cooperate advantageously to implement, in accordance with the principles of the invention, the desired observability, and control to designers to tune the device, e.g.

Abstract: A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

Abstract: A DMT signal conforming to a first DMT standard (e.g., the full-rate G.dmt standard based on 255 tones) is sampled at a sampling rate for the first DMT standard, filtered to attenuate a subset of the tones of the first DMT standard (e.g., all G.dmt tones above tone #127), and subsampled (e.g., 2:1) to provide a subsampled, filtered signal that can be further processed using components designed to operate under a second, different DMT standard (e.g., the half-rate G.lite standard based on 127 tones). As such, a conventional half-rate G.lite DMT transceiver can be modified (e.g., by changing the downstream sampling rate from 1.104 MHz to 2.208 MHz and adding an appropriate low-pass filter and decimator) for configuration in a full-rate G.dmt DMT system.

Abstract: A unique real time tuning (RTT) process is employed for obtaining the desired optimum device parameter adjustments. The RTT parameter adjustment process is utilized with IP phone or other device chipsets as desired. In one embodiment, RTT provides a graphical user interface to a digital signal processor (DSP), or the like, on the device chipset allowing for observation, evaluation and control of the device parameters in real time. The real time exchange of the device parameter information between the device and an external workstation, e.g., a personal computer or the like, is provided by a User Datagram Protocol (UDP) that runs on a controller on the device, e.g., an ARM processor or the like. In this example, the unique combination of the RTT, UDP and DSP cooperate advantageously to implement, in accordance with the principles of the invention, the desired observability, and control to designers to tune the device, e.g.

Abstract: Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. Depending on the means squared error (MSE) between the input and the output of the slicer, the slicer tables continue to be updated, and the feed-forward and feed-backward equalizer filters are selectively adjusted in accordance with the channel impulse response ascertained at each of the slicing levels.

Abstract: Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. To mitigate the effects of robbed bit signaling that may be employed in the digital transmission network, an array of slicers is provided to determine which bit position is being robbed and to base level learning on samples obtained from the non-robbed positions.

Abstract: The present invention combines the inherent advantages of half-rate and full-rate DMT modulation schemes. A DMT transceiver of a DSL modem includes a variable bandwidth receiver filter which adjusts the bandwidth of the signal received by a DMT receiver. The variable bandwidth receiver filter may be analog or digital in design. The DMT transceiver further includes an AM radio signal detector and useful bandwidth detector which can detect the presence of AM radio interference (e.g., strong AM radio signals) on the service line. Then, either automatically or with user confirmation, the DMT transceiver adaptively adjusts its bandwidth from, e.g., a full-rate DMT mode to a half-rate DMT mode, or from using all sub-channels to using less than all available sub-channels, by changing the parameters of the variable bandwidth receiver filter, in accordance with the principles of the present invention. A highest number of sub-channel used may be transmitted to a corresponding DMT transceiver at the other end (e.g.

Abstract: A so-called post equalization echo canceler is utilized in conjunction with transmitter and receiver data timing synchronization to enhance tracking of the echo path impulse response and convergence of the transversal filter in the post equalization echo canceler. This is realized by employing the equalization error in the receiver to adapt coefficients of the post equalization echo canceler transversal filter, in conjunction, with the transmitter and receiver data timing synchronization. The timing synchronization is realized by using sample rate conversion of the transmit sample rate to the receive sample rate and, in one example, variable phase interpolation of the converted timing signal. The receiver timing is recovered, and a phase error signal generated by the timing recovery unit is advantageously employed to adjust a variable phase interpolator in the receiver and a variable phase interpolator in a path supplying the transmitter signal to an input of the post equalization echo canceler.

Abstract: Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. Thereafter, the analog modem's equalizer may be fine tuned in accordance with the channel impulse response ascertained at each slicing level.

Abstract: A multiple tone detector includes n tone detectors, each detecting one of n distinct tones, where n.gtoreq.2, and a background detector which generates a measure of accumulative background energy E.sub.avg in a frequency band or bands which do not include at least a subset of the n tones. The output of the background detector is applied to a smoothing filter, which generates the accumulative background energy measure E.sub.avg for a current frame as a weighted sum of the background detector output for the current frame and the background energy measure E.sub.avg from a previous frame. A parameter controlling response time of the smoothing filter is varied depending upon whether or not speech is determined to be present in the background portion of the input signal. A processor uses the energy measures from the n tone detectors and the background detector to compute n ratios, where a given ratio is the ratio of the energy measure of the ith tone to the accumulative background energy measure E.sub.avg.

Abstract: A digital speech communication system having improved synchronization. The present digital speech communication system reduces the unit of degradation to a single speech sample, rather than a multi-sample frame, while maintaining the bit rate efficiency of the DSVD system and other systems where speech is encoded into large blocks and is subject to variable delay and mismatched clocks. The basic unit that is dropped or artificially inserted by the receiver, if the buffer overflows or empties, respectively, is reduced to a single speech sample. The speech frames produced by the demultiplexer are written into a frame buffer, in units of frames, at a rate determined by the clock signal, S2, that is extracted from the received signal by a timing recovery function in the modem. In accordance with the present invention, the frames are read out of the buffer into the decoder using the same extracted clock signal, S2. In this manner, once the buffer is partially full, the frame buffer will not overflow or empty.