Patents by Inventor Bahram Ahanin

Bahram Ahanin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6897679
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: May 24, 2005
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 6759870
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 6, 2004
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, Bahram Ahanin, Craig Schilling Lytle, Francis B. Heile, Bruce B. Pedersen, Kerry Veenstra
  • Publication number: 20040066212
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Application
    Filed: January 31, 2003
    Publication date: April 8, 2004
    Applicant: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Publication number: 20030128052
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Application
    Filed: February 20, 2003
    Publication date: July 10, 2003
    Applicant: ALTERA CORPORATION, a corporation of Delaware
    Inventors: Richard G. Cliff, Bahram Ahanin, Craig Schilling Lytle, Francis B. Heile, Bruce B. Pedersen, Kerry Veenstra
  • Publication number: 20020130681
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Application
    Filed: August 22, 2001
    Publication date: September 19, 2002
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 6278291
    Abstract: A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: August 21, 2001
    Assignee: Altera Corporation
    Inventors: Cameron McClintock, William Leong, Richard G. Cliff, Bahram Ahanin
  • Patent number: 6134173
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: October 17, 2000
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 6127846
    Abstract: A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: October 3, 2000
    Assignee: Altera Corporation
    Inventors: Cameron McClintock, William Leong, Richard G. Cliff, Bahram Ahanin
  • Patent number: 6064599
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs") The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: May 16, 2000
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 6028808
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: February 22, 2000
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 6023439
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: February 8, 2000
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 6018490
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: January 25, 2000
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 5900743
    Abstract: A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: May 4, 1999
    Assignee: Altera Corporation
    Inventors: Cameron McClintock, William Leong, Richard G. Cliff, Bahram Ahanin
  • Patent number: 5883850
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: March 16, 1999
    Assignee: Altera Corporation
    Inventors: Fung Fung Lee, Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 5848005
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: December 8, 1998
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 5838628
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: November 17, 1998
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 5828229
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: October 27, 1998
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron McClintock, William Leong, James Allen Watson, Joseph Huang, Bahram Ahanin, Chiakang Sung, Wanli Chang
  • Patent number: 5812479
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: September 22, 1998
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 5764583
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: June 9, 1998
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: RE38651
    Abstract: A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: November 9, 2004
    Assignee: Altera Corporation
    Inventors: Chiakang Sung, Wanli Chang, Joseph Huang, Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Bahram Ahanin