Abstract: An electronic component package, including: a multilayer ceramic or glass-ceramic substrate formed of a stacked plurality of generally parallel signal and insulating layers, each of the signal layers comprising an electrically conductive pattern; a cavity in a surface of the substrate sized to accommodate an electronic component with a planar surface of the electronic component disposed substantially planar with the surface of the substrate; and a plurality of electrical conductors extending from the surface of the substrate to selected ones of the signal layers for connecting the electronic component to the signal layers. Thin film wiring is provided for connecting the electronic component to the substrate.

Abstract: A resist mark comprising two layers of resist, one of which is saturated with a diluant which does not dissolve the other. In one embodiment, the two layers of resist are applied upon a substrate, the first layer of which is more soluble in a developer. The second layer is said saturated resist and the first layer is non-saturated. This composite is preferably used to form a relief mask with recessed sidewalls used in lift-off processes.

Abstract: A resist mask comprising two layers of resist, one of which is saturated with a dilutant which does not dissolve the other. In one embodiment, the two layers of resist are applied upon a substrate, the first layer of which is more soluble in a developer. The second layer is said saturated resist and the first layer is non-saturated. This composite is preferably used to form a relief mask with recessed sidewalls used in lift-off processes.

Abstract: A resist mask comprising two layers of resist, one of which is saturated with a dilutant which does not dissolve the other. In one embodiment, the two layers of resist are applied upon a substrate, the first layer of which is more soluble in a developer. The second layer is said saturated resist and the first layer is non-saturated. This composite is preferaly used to form a relief mask with recessed sidewalls used in lift-off processes.

Abstract: A method of forming extremely small impurity regions within other impurity regions without the need for providing critical masks. In the preferred embodiment this is achieved by forming an undercut band within masking layers atop a substrate to define a first impurity region, such as the base region of a bipolar transistor. After this region is formed by the introduction of impurities, the undercut is filled-in by a chemical vapor deposition process. A blocking mask may then be used for the formation of the second impurity region, in this case the emitter, within the first region. The window of the second region is defined by the filled-in band, thereby insuring a selected distance between the peripheries of said first and second impurity regions. The same mask may also be used to form other self-aligned regions with the first region.

Abstract: An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated area which remain uncovered by the photoresist.

Abstract: A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed.

Abstract: The method for making patterned resist masks having minimum opening dimensions. The mask is prepared initially using standard photo or electron beam lithography techniques to yield the smallest aperture dimensions consistent with the state-of-the-art. Then, the resulting mask is placed within a chamber containing an atmosphere of resist solvent vapor. The vapor is absorbed by the patterned resist mask causing controlled resist reflow which uniformly reduces the dimensions of the resist openings by an amount determined by time, temperature, resist thickness, resist type and solvent used.

Abstract: An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated areas which remain uncovered by the photoresist.