Abstract: The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.