Patents by Inventor Bai-Mei Chang

Bai-Mei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10153288
    Abstract: A non-volatile memory having a double metal layout is provided that includes a first fuse fabricated on a first conductive layer of the integrated circuit, a second fuse fabricated on a second conductive layer of the integrated circuit, and a transistor fabricated on front-end-of-the-line (FEOL) structure of the integrated circuit. A first memory cell of the non-volatile memory is provided by a first memory circuit comprising the first fuse and the transistor, and a second memory cell of the non-volatile memory is provided by a second memory circuit comprising the second fuse and the transistor.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Sheng Chang, Bai-Mei Chang, Shao-Yu Chou, Liang Chuan Chang
  • Publication number: 20170345827
    Abstract: A non-volatile memory having a double metal layout is provided that includes a first fuse fabricated on a first conductive layer of the integrated circuit, a second fuse fabricated on a second conductive layer of the integrated circuit, and a transistor fabricated on front-end-of-the-line (FEOL) structure of the integrated circuit. A first memory cell of the non-volatile memory is provided by a first memory circuit comprising the first fuse and the transistor, and a second memory cell of the non-volatile memory is provided by a second memory circuit comprising the second fuse and the transistor.
    Type: Application
    Filed: February 2, 2017
    Publication date: November 30, 2017
    Inventors: Meng-Sheng Chang, Bai-Mei Chang, Shao-Yu Chou, Liang Chuan Chang
  • Patent number: 9805815
    Abstract: A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hung Chen, Liang Chuan Chang, Wei-Fen Pai, Bai-Mei Chang, Shao-Yu Chou, Ren-Fen Tsui, Dian-Sheg Yu, Shih-Guo Shen