Abstract: A power converter is disclosed. The power converter includes a positive power supply, an output node, first, second, and third high side transistors serially connected between the positive power supply and the output node, and a high side bias voltage generator configured to generate a high side bias voltage. A gate of the second high side transistor is connected to the high side bias voltage generator. The power converter also includes a signal driver configured to selectively connect a gate of the first transistor to either the positive power supply or the high side bias voltage generator, a switch configured to selectively connect a gate of the third transistor to the high side bias voltage generator, and a capacitor connected to the gate of the third transistor and to a source of the second high side transistor.

Abstract: A circuit. In one aspect, the circuit includes a power input terminal and an output terminal, a high-side circuit coupled between the power input terminal and the output terminal, where the high-side circuit includes a first plurality of serially connected switches, and a low-side circuit coupled between the output terminal and a ground, where the low-side circuit includes a second plurality of serially connected switches, where a first voltage between the power input terminal and the output terminal is distributed across the first plurality of serially connected switches, where a second voltage between the output terminal and the ground is distributed across the second plurality of serially connected switches. In another aspect, the high-side and low-side circuits are arranged to limit a maximum voltage applied to each of the first plurality of switches and second plurality of switches to a fraction of a voltage at the power input terminal.

Abstract: Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.

Abstract: A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supply operable to provide power to the logic core of the PLD, such as the programmable logic blocks, routing structure, and volatile configuration memory. The internal power supply powers down the logic core in response to assertion of a power-down signal, while power is maintained to other circuitry of the PLD.

Abstract: A programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide distributed random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure. In one embodiment, there are at least twice as many logic blocks in the first plurality of logic blocks than in the second plurality of logic blocks. In another embodiment, the first and second plurality of logic blocks are arranged in one or more rows, and the programmable logic device includes one or more rows of embedded block RAM.

Abstract: Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, with the reference circuit providing default voltage levels for the second plurality of reference signals if a first control signal is asserted. An input/output circuit, coupled to the reference circuit and to an output driver, receives the second plurality of reference signals to control the output driver to provide an output signal, with the output driver operated with the default voltage levels if the first control signal is asserted.

Abstract: A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

Abstract: Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks.

Abstract: Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.

Abstract: Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery circuit. The programmable interface further includes programmable input/output buffers and embedded memory to allow the programmable logic device to support a wide range of input/output interface standards.

Abstract: Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect (PCI) clamps, single-ended buffers without PCI clamps, and differential buffers without PCI clamps. By distributing these different types of I/O buffers around the periphery of the device, a relatively low-cost device can be implemented with relatively small I/O buffers that collectively provide all of the I/O signaling functionality of prior-art devices that are implemented with relatively large, all-purpose I/O buffers, each of which supports the full range of I/O signaling options available on the device.

Abstract: A field programmable gate array (FPGA) has plural columns of run-time memory provided in each of one or more partitions. Each column of run-time memory has a plurality of configurable memory blocks (CMB's). Each CMB is programmably configurable at least into a shallow-and-widest mode where data words have a maximum bit width and into a deep-and-narrowest mode where data words have a minimum bit width. Each CMB spans plural interconnect buses and the bits of its widest data words are distributed among the spanned interconnect buses. When a deep-and-narrow mode is invoked, CMB's of alternate columns operate in complementary fashion so that bits of narrowed words from one CMB move through a first subset of the interconnect buses while bits of narrowed words from a second CMB, in an alternate column, move through a second subset of the interconnect buses, where the second subset is mutually exclusive of the first subset of the interconnect buses.

Abstract: A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block).

Abstract: A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.

Abstract: A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions.

Abstract: A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.

Abstract: A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block).

Abstract: An integrated capacitor structure includes first and second, conductive semiconductor portions spaced apart from one another where the first and second semiconductor portion are both of a same conductivity type (both N or both P). The integrated capacitor structure may be formed using same processes as are used for fabricating gate insulator and gate electrode parts of neighboring MOS transistors in a same integrated circuit.

Abstract: A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.

Abstract: A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.