Abstract: Disclosed are an apparatuses and methods for minimum energy tracking loop that includes an oscillator to imitate a threshold path of a load system and automatically adjust a clock frequency as a supply voltage to the load system is changed, a voltage regulator configured to supply a power, an energy sensing unit which is connected to the oscillator and the voltage regulator and calculates a proportional energy proportional to a total energy consumed by the load system at a specific supply voltage, a minimum energy finder to find a minimum energy point of the load system by monitoring the calculated proportional energy proportional to the total energy at a plurality of supply voltages, a buck converter to supply a power to the load system with a supply voltage at which the load system operates with a minimum energy when the minimum energy point is found in the minimum energy finder.

Abstract: An exemplary embodiment of the present disclosure relates to a rail-to-rail class-AB buffer amplifier using compact adaptive biasing, and the rail-to-rail class-AB buffer amplifier using compact adaptive biasing includes an input stage generating a differential current pair based on a voltage difference between a first input signal and a second input signal, an amplification stage outputting a driving signal based on the differential current pair, an output stage connected to the amplification stage and outputting an output signal, an auxiliary current source switch which is on/off based on the driving signal of the amplification stage, and a current mirroring unit generating bias current and outputting the generated bias current to the input stage when the auxiliary current source switch is on.

Abstract: Disclosed are an apparatuses and methods for minimum energy tracking loop that includes an oscillator to imitate a threshold path of a load system and automatically adjust a clock frequency as a supply voltage to the load system is changed, a voltage regulator configured to supply a power, an energy sensing unit which is connected to the oscillator and the voltage regulator and calculates a proportional energy proportional to a total energy consumed by the load system at a specific supply voltage, a minimum energy finder to find a minimum energy point of the load system by monitoring the calculated proportional energy proportional to the total energy at a plurality of supply voltages, a buck converter to supply a power to the load system with a supply voltage at which the load system operates with a minimum energy when the minimum energy point is found in the minimum energy finder.

Abstract: The present disclosure relates to a buck converter which includes a voltage converter configured to convert an input voltage into an output voltage by a driving signal, a compensator configured to generate an error compensation signal by receiving a feedback signal defined from the output voltage, an active ramp controller configured to generate a ramp signal by adjusting a ramp bias voltage when load transient occurs, and an output voltage controller configured to adjust the output voltage using the ramp signal and the error compensation signal.

Abstract: A PWM buck converter includes a first P-type transistor having a drain terminal connected to a first node, a first N-type transistor having a drain terminal connected to the first node, and a gate driver configured to apply a first gate voltage to a first gate terminal of the first P-type transistor and apply a second gate voltage to a second gate terminal of the first N-type transistor. The gate driver includes a first buffer configured to generate the first gate voltage applied to the gate terminal of the first P-type transistor, a second buffer configured to generate the second gate voltage applied to the gate terminal of the first N-type transistor, and a capacitor configured to accumulate a portion of electrical charges supplied from the first buffer to the first P-type transistor, and supply the accumulated electrical charges to the gate terminal of the first N-type transistor.

Abstract: A PWM buck converter includes a first P-type transistor having a drain terminal connected to a first node, a first N-type transistor having a drain terminal connected to the first node, and a gate driver configured to apply a first gate voltage to a first gate terminal of the first P-type transistor and apply a second gate voltage to a second gate terminal of the first N-type transistor. The gate driver includes a first buffer configured to generate the first gate voltage applied to the gate terminal of the first P-type transistor, a second buffer configured to generate the second gate voltage applied to the gate terminal of the first N-type transistor, and a capacitor configured to accumulate a portion of electrical charges supplied from the first buffer to the first P-type transistor, and supply the accumulated electrical charges to the gate terminal of the first N-type transistor.

Abstract: The present disclosure relates to a buck converter which includes a voltage converter configured to convert an input voltage into an output voltage by a driving signal, a compensator configured to generate an error compensation signal by receiving a feedback signal defined from the output voltage, an active ramp controller configured to generate a ramp signal by adjusting a ramp bias voltage when load transient occurs, and an output voltage controller configured to adjust the output voltage using the ramp signal and the error compensation signal.

Abstract: A flip-flop includes a conditional boosting stage, a pulse generator and a latch. The conditional boosting stage includes a boosting capacitor, and is configured to pre-charge the boosting capacitor in accordance with a previous output signal and boost a node connected to the boosting capacitor upon a level the previous output signal being different from a level of a current input signal. The pulse generator is configured to generate a pulsed signal in accordance with transitions of a clock signal. The latch configured is to latch the current input signal to a current output signal in accordance with the pulsed signal.

Abstract: A flip-flop includes a conditional boosting stage, a pulse generator and a latch. The conditional boosting stage includes a boosting capacitor, and is configured to pre-charge the boosting capacitor in accordance with a previous output signal and boost a node connected to the boosting capacitor upon a level of the previous output signal being different from a level of a current input signal. The pulse generator is configured to generate a pulsed signal in accordance with transitions of a clock signal. The latch configured is to latch the current input signal to a current output signal in accordance with the pulsed signal.

Abstract: A delta-sigma modulator includes a first integrator configured to integrate a sum of an input signal and a first feedback signal, a second integrator configured to integrate a sum of an output value of the first integrator and a second feedback signal, a first FIR filter circuit configured to perform a first FIR filtering on an output modulation signal and a delay modulation signal and feeds back the signals to stage prior to the first integrator, and a second FIR filter circuit configured to perform a second FIR filtering on the output modulation signal and the delay modulation signal and feeds back the signals to a stage prior to the second integrator.

Abstract: A delta-sigma modulator includes a first integrator configured to integrate a sum of an input signal and a first feedback signal, a second integrator configured to integrate a sum of an output value of the first integrator and a second feedback signal, a first FIR filter circuit configured to perform a first FIR filtering on an output modulation signal and a delay modulation signal and feeds back the signals to stage prior to the first integrator, and a second FIR filter circuit configured to perform a second FIR filtering on the output modulation signal and the delay modulation signal and feeds back the signals to a stage prior to the second integrator.

Abstract: A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.

Abstract: A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.

Abstract: A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage level at the selected output terminal bidirectionally transitions between a first voltage level and a second voltage level. A voltage level at a non-selected output terminal unidirectionally transitions between the first voltage level and the second voltage level.

Abstract: A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

Abstract: A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.