Abstract: A digital logic circuit is provided which eliminates excessive power consumption while providing high speed transitions between logic states. The digital logic circuit includes a pull-down device coupled to an input line. The digital logic circuit further comprises a weak pull-up device and a strong pull-up device coupled to the pull-down device at a node. A means for providing a signal on an output line of the programmable logic device is coupled to the pull-down device and the pull-up devices. The weak pull-up device holds the node high if the pull-down device is in an off state. However, if the pull-down device is in an on state, the strong pull-up device is also turned on, thereby providing a stable intermediate voltage on the node. A feedback path from the output line controls the state of the strong pull-up device.