Abstract: A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and ?V1 when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source VDD and a control low power source VNEG. The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or ?V1 if IN is high when EN is high. Only single type VT transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.

Abstract: Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. The read assist circuit includes a first drive device for driving a wordline of the semiconductor memory device to a wordline driving voltage. The first drive device operates at a first current. The read assist circuit also includes a second drive device for maintaining the wordline of the semiconductor memory device at the wordline driving voltage. The second drive device operates at a second current lower than the first current.

Abstract: Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. The read assist circuit includes a first drive device for driving a wordline of the semiconductor memory device to a wordline driving voltage. The first drive device operates at a first current. The read assist circuit also includes a second drive device for maintaining the wordline of the semiconductor memory device at the wordline driving voltage. The second drive device operates at a second current lower than the first current.

Abstract: Device and a method of configuring a voltage level shifter is disclosed. The device includes a traditional level shifter circuit (TLSC), a first control circuit (FCC) cross-coupled to a second control circuit (SCC). The FCC is coupled to receive an inverse of an input at a first input node and provide a first output at a first output node. The SCC is coupled to receive the input at a second input node and provide a second output at a second output node and the TLSC is configured to provide an output at an output node in response to the first output received at the first output node and the second output received at the second output node. A first power source is configured to provide a first power supply voltage to the TLSC, the FCC and the SCC. The output is latched to track the input. The TLSC, the FCC and the SCC are coupled to a ground reference node.

Abstract: A system and method for testing performance of a plurality of memory modules includes generating a clock signal at a set frequency and sending the clock signal to the memory modules. An initial data pattern is sent to an input of a first memory module. A subsequent data pattern received from the first memory module is delayed by a predetermined delay time and sent to an input of a last memory module. The initial data pattern and the subsequent data pattern received from the output of the last memory module are compared and a performance of the memory modules is also calculated.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.

Abstract: A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and ?V1 when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source VDD and a control low power source VNEG. The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or ?V1 if IN is high when EN is high. Only single type VT transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.

Abstract: Bandgap reference voltage generator circuits are provided that include an operational amplifier, a current mirror configured to be coupled to a supply voltage, a first branch coupled to the current mirror, a second branch coupled to the first branch, a third branch coupled to the second branch and a fourth branch. The operational amplifier includes a first input configured to receive a first voltage and a second input configured to receive a second voltage, and an output that is configured to generate an output voltage. The current mirror is configured to generate a third voltage and a first current. The first branch is configured to receive a second current that is a first portion of the first current, the second branch is configured to receive a third current that is a second portion of the first current, the third branch is configured to receive a fourth current that is a third portion of the first current, and the fourth branch is configured to receive a fifth current generated by the current mirror.

Abstract: A methodology for the simulation of semiconductor memory devices that exhibits improved accuracy and speed, and the apparatus performing the methodology are disclosed. Embodiments may include determining a state of a bitcell of an integrated circuit (IC) design, determining a first threshold voltage for the bitcell based on the state of the bitcell, and simulating electrical characteristics of the bitcell according to the first threshold voltage to verify the IC design.

Abstract: A semiconductor device for storing data includes a memory cell. The memory cell comprises a plurality of transistors. A trimmable sense amplifier is electrically connected to the memory cell. The trimmable sense amplifier is configured to provide variable current to said memory cell. A charge pump is also electrically connected to the memory cell. The charge pump includes a plurality of diodes disposed in series with one another. The charge pump includes an input for receiving an input voltage and an output for providing an output voltage greater than the input voltage to the memory cell.

Abstract: A semiconductor device for storing data includes a memory cell. The memory cell comprises a plurality of transistors. A trimmable sense amplifier is electrically connected to the memory cell. The trimmable sense amplifier is configured to provide variable current to said memory cell. A charge pump is also electrically connected to the memory cell. The charge pump includes a plurality of diodes disposed in series with one another. The charge pump includes an input for receiving an input voltage and an output for providing an output voltage greater than the input voltage to the memory cell.

Abstract: A methodology for the simulation of semiconductor memory devices that exhibits improved accuracy and speed, and the apparatus performing the methodology are disclosed. Embodiments may include determining a state of a bitcell of an integrated circuit (IC) design, determining a first threshold voltage for the bitcell based on the state of the bitcell, and simulating electrical characteristics of the bitcell according to the first threshold voltage to verify the IC design.

Abstract: A system and method for testing performance of a plurality of memory modules includes generating a clock signal at a set frequency and sending the clock signal to the memory modules. An initial data pattern is sent to an input of a first memory module. A subsequent data pattern received from the first memory module is delayed by a predetermined delay time and sent to an input of a last memory module. The initial data pattern and the subsequent data pattern received from the output of the last memory module are compared and a performance of the memory modules is also calculated.

Abstract: Bandgap reference voltage generator circuits are provided that include an operational amplifier, a current mirror configured to be coupled to a supply voltage, a first branch coupled to the current mirror, a second branch coupled to the first branch, a third branch coupled to the second branch and a fourth branch. The operational amplifier includes a first input configured to receive a first voltage and a second input configured to receive a second voltage, and an output that is configured to generate an output voltage. The current mirror is configured to generate a third voltage and a first current. The first branch is configured to receive a second current that is a first portion of the first current, the second branch is configured to receive a third current that is a second portion of the first current, the third branch is configured to receive a fourth current that is a third portion of the first current, and the fourth branch is configured to receive a fifth current generated by the current mirror.

Abstract: A fuse circuit having a fuse unit cell containing two fuses. In the program/write mode, only one of the fuses in the fuse unit cell will be blown. In read mode, since only one fuse is blown, the current that goes through the two fuses in the fuse unit cell will be very small. Hence, the read power consumption for the fuse circuit is also very small and its sensing speed is also very high.

Abstract: A fuse circuit having a fuse unit cell containing two fuses. In the program/write mode, only one of the fuses in the fuse unit cell will be blown. In read mode, since only one fuse is blown, the current that goes through the two fuses in the fuse unit cell will be very small. Hence, the read power consumption for the fuse circuit is also very small and its sensing speed is also very high.