Abstract: For direct chip-on-array for a multi-dimensional transducer array, the generally rigid and conductive dematching layer is extended beyond a footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides for electrical connection to the elements of the array and I/O pads for connections (e.g., flex-to-dematching layer) to the ultrasound imaging system. By using the dematching layer rigidity, the ASIC may be protected during formation of the acoustic stack. By using the dematching layer conductivity, any mis-alignment is compensated by the routing through the dematching layer, and/or a large flat region is provided for I/O, allowing for good low temperature asperity contact connections with larger area than flip-chip solder bumps. By providing the I/O for the system connections on a different side of the dematching layer than the ASIC, a large keep-out distance due to underfill may be avoided.

Abstract: For direct chip-on-array for a multi-dimensional transducer array, the generally rigid and conductive dematching layer is extended beyond a footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides for electrical connection to the elements of the array and I/O pads for connections (e.g., flex-to-dematching layer) to the ultrasound imaging system. By using the dematching layer rigidity, the ASIC may be protected during formation of the acoustic stack. By using the dematching layer conductivity, any mis-alignment is compensated by the routing through the dematching layer, and/or a large flat region is provided for I/O, allowing for good low temperature asperity contact connections with larger area than flip-chip solder bumps. By providing the I/O for the system connections on a different side of the dematching layer than the ASIC, a large keep-out distance due to underfill may be avoided.

Abstract: For direct chip-on-array for a multi-dimensional transducer array, the generally rigid and conductive dematching layer is extended beyond a footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides for electrical connection to the elements of the array and I/O pads for connections (e.g., flex-to-dematching layer) to the ultrasound imaging system. By using the dematching layer rigidity, the ASIC may be protected during formation of the acoustic stack. By using the dematching layer conductivity, any mis-alignment is compensated by the routing through the dematching layer, and/or a large flat region is provided for I/O, allowing for good low temperature asperity contact connections with larger area than flip-chip solder bumps. By providing the I/O for the system connections on a different side of the dematching layer than the ASIC, a large keep-out distance due to underfill may be avoided.

Abstract: In a chip-on-array approach, acoustic and electronic modules are separately formed. The acoustic stack is connected to one interposer, and the electronics are connected to another interposer. Different connection processes (e.g., using low temperature bonding for the acoustic stack and higher temperature-based interconnect for the electronics) may be used. This arrangement may allow for different pitches of the transducer elements and the I/O of the electronics by staggering vias in the interposers. The two interposers are then connected to form the chip-on-array.

Abstract: In a chip-on-array approach, acoustic and electronic modules are separately formed. The acoustic stack is connected to one interposer, and the electronics are connected to another interposer. Different connection processes (e.g., using low temperature bonding for the acoustic stack and higher temperature-based interconnect for the electronics) may be used. This arrangement may allow for different pitches of the transducer elements and the I/O of the electronics by staggering vias in the interposers. The two interposers are then connected to form the chip-on-array.

Abstract: For direct chip-on-array for a multi-dimensional transducer array, the generally rigid and conductive dematching layer is extended beyond a footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides for electrical connection to the elements of the array and I/O pads for connections (e.g., flex-to-dematching layer) to the ultrasound imaging system. By using the dematching layer rigidity, the ASIC may be protected during formation of the acoustic stack. By using the dematching layer conductivity, any mis-alignment is compensated by the routing through the dematching layer, and/or a large flat region is provided for I/O, allowing for good low temperature asperity contact connections with larger area than flip-chip solder bumps. By providing the I/O for the system connections on a different side of the dematching layer than the ASIC, a large keep-out distance due to underfill may be avoided.

Abstract: An ultrasound transducer used in an ultrasound system and a method of manufacturing the same are disclosed. The ultrasound transducer is manufactured by forming a backing block including a plurality of surfaces; forming a piezoelectric layer including a first portion formed on the backing block to be in contact therewith and a second portion extending from the first portion; electrically connecting a plurality of pins to the second portion by attaching a connector having the plurality of pins for electrical connection with at least one of a transmitting unit and a receiving unit of an ultrasound system to at least one surface of the plurality of surfaces of the backing block; cutting the first portion and the second portion of the piezoelectric layer into a plurality of piezoelectric elements, wherein each of the plurality of piezoelectric elements is connected to a corresponding one of the plurality of pins of the connector; and forming a ground layer connected to the piezoelectric layer.

Abstract: For transducer connection to an integrated circuit, a silicon or other wafer-based chip is processed to provide signal routing, such as altering the pitch using wafer process deposited conductors. This chip or silicon interposer may be more simply re-designed to relate the pitch of an array to the integrated circuit I/Os, avoiding redesign of the integrated circuit.

Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.

Abstract: In a chip-on-array approach, acoustic and electronic modules are separately formed. The acoustic stack is connected to one interposer, and the electronics are connected to another interposer. Different connection processes (e.g., using low temperature bonding for the acoustic stack and higher temperature-based interconnect for the electronics) may be used. This arrangement may allow for different pitches of the transducer elements and the I/O of the electronics by staggering vias in the interposers. The two interposers are then connected to form the chip-on-array.

Abstract: An ultrasound transducer used in an ultrasound system and a method of manufacturing the same are disclosed. The ultrasound transducer is manufactured by forming a backing block including a plurality of surfaces; forming a piezoelectric layer including a first portion formed on the backing block to be in contact therewith and a second portion extending from the first portion; electrically connecting a plurality of pins to the second portion by attaching a connector having the plurality of pins for electrical connection with at least one of a transmitting unit and a receiving unit of an ultrasound system to at least one surface of the plurality of surfaces of the backing block; cutting the first portion and the second portion of the piezoelectric layer into a plurality of piezoelectric elements, wherein each of the plurality of piezoelectric elements is connected to a corresponding one of the plurality of pins of the connector; and forming a ground layer connected to the piezoelectric layer.

Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.

Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.

Abstract: In one embodiment, a semiconductor device comprising, a substrate comprising a wiring layer, a first conductive shielding layer disposed on the substrate and electrically isolated from the wiring layer, the first conductive shielding layer comprising a first bonding surface and a first end surface extending from the first bonding surface, a semiconductor chip disposed on the first conductive shielding layer, a molding member disposed over the first conductive shielding layer to cover the semiconductor chip, a second conductive shielding layer disposed over the first conductive shielding layer and the molding member, the second conductive shielding layer comprising a second bonding surface and a second end surface extending from the second bonding surface, and a bonding portion disposed between the first and second bonding surfaces, the bonding portion comprising a top surface and a bottom surface opposite to the top surface.

Abstract: A passive element package includes a first substrate, first passive elements disposed on the first substrate, a second substrate disposed on the first passive elements, second passive elements disposed on the second substrate, and a sealant that seals the first passive elements and the second passive elements. The passive element package can reduce the size of a semiconductor module that includes the passive element package.

Abstract: A printed circuit board is provided. The printed circuit board comprises a base substrate comprising a chip mounting region on an upper surface thereof, a plurality of connection pad structures in the chip mounting region, and an extension pattern on the base substrate, spaced from each of two adjacent connection pad structures from among the plurality of connection pad structures, and extending along the two adjacent connection pad structures. Upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern.

Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.

Abstract: In one embodiment, a semiconductor device comprising, a substrate comprising a wiring layer, a first conductive shielding layer disposed on the substrate and electrically isolated from the wiring layer, the first conductive shielding layer comprising a first bonding surface and a first end surface extending from the first bonding surface, a semiconductor chip disposed on the first conductive shielding layer, a molding member disposed over the first conductive shielding layer to cover the semiconductor chip, a second conductive shielding layer disposed over the first conductive shielding layer and the molding member, the second conductive shielding layer comprising a second bonding surface and a second end surface extending from the second bonding surface, and a bonding portion disposed between the first and second bonding surfaces, the bonding portion comprising a top surface and a bottom surface opposite to the top surface.

Abstract: A printed circuit board is provided. The printed circuit board comprises a base substrate comprising a chip mounting region on an upper surface thereof, a plurality of connection pad structures in the chip mounting region, and an extension pattern on the base substrate, spaced from each of two adjacent connection pad structures from among the plurality of connection pad structures, and extending along the two adjacent connection pad structures. Upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern.

Abstract: Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag3Sn. A method of manufacturing the semiconductor device package may include forming a bonding layer, which bonds a semiconductor chip to a substrate, by using a mixed paste including metal particles and a solder material. The bonding layer may be formed by forming an intermetallic compound, which is formed by heating the mixed paste to react the metal particles with the solder material.