Patents by Inventor Bailing Liu
Bailing Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240142546Abstract: Disclosed is a method for testing and evaluating a short-circuit withstand capability of a press-pack power component.Type: ApplicationFiled: October 11, 2023Publication date: May 2, 2024Inventors: Hui LI, Renkuan LIU, Ran YAO, Wei LAI, Zeyu DUAN, Zheyan ZHU, Bailing ZHOU, Siyu CHEN, Jinyuan LI, Zhongyuan CHEN
-
Patent number: 11469254Abstract: An array substrate, a method of manufacturing an array substrate, a display panel, and an electronic device are provided. The array substrate includes a display area and a peripheral area; the display area includes a pixel region, the pixel region includes a first thin film transistor, and the first thin film transistor includes a first active layer; the peripheral area includes a second thin film transistor, and the second thin film transistor includes a second active layer; and the first active layer includes a material of oxide semiconductor, and the second active layer includes a material of poly-silicon semiconductor.Type: GrantFiled: April 8, 2019Date of Patent: October 11, 2022Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., Beijing BOE Technology Development Co., Ltd.Inventors: Peng Liu, Fuqiang Li, Jun Fan, Bailing Liu, Jianjun Zhang, Yusheng Liu, Mei Li
-
Patent number: 11361703Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.Type: GrantFiled: March 28, 2019Date of Patent: June 14, 2022Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng Liu, Bailing Liu, Fuqiang Li, Zhichong Wang, Jing Feng, Xinglong Luan
-
Patent number: 11328652Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.Type: GrantFiled: March 28, 2019Date of Patent: May 10, 2022Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng Liu, Bailing Liu, Fuqiang Li, Zhichong Wang, Jing Feng, Xinglong Luan
-
Publication number: 20210408081Abstract: An array substrate, a method of manufacturing an array substrate, a display panel, and an electronic device are provided. The array substrate includes a display area and a peripheral area; the display area includes a pixel region, the pixel region includes a first thin film transistor, and the first thin film transistor includes a first active layer; the peripheral area includes a second thin film transistor, and the second thin film transistor includes a second active layer; and the first active layer includes a material of oxide semiconductor, and the second active layer includes a material of poly-silicon semiconductor.Type: ApplicationFiled: April 8, 2019Publication date: December 30, 2021Inventors: Peng LIU, Fuqiang LI, Jun FAN, Bailing LIU, Jianjun ZHANG, Yusheng LIU, Mei LI
-
Patent number: 11200649Abstract: An image processing method provided by embodiments of the present disclosure includes acquiring, two adjacent frames of original images from a video image data stream; extracting a feature element that produces smear from the two adjacent frames of the original images; generating a reconstructed image frame that does not comprise the feature element by using the two adjacent frames of the original images and the feature element; and inserting the reconstructed image frame between the two adjacent frames of the original images.Type: GrantFiled: November 19, 2018Date of Patent: December 14, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Haifeng Bi, Xin Wang, Yan Fang, Wenke Li, Yufeng Bao, Bailing Liu, Shun Zhao, Lifeng Chen
-
Publication number: 20210241673Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a fist pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.Type: ApplicationFiled: March 28, 2019Publication date: August 5, 2021Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng LIU, Bailing LIU, Fuqiang LI, Zhichong WANG, Jing FENG, Xinglong LUAN
-
Publication number: 20210097658Abstract: An image processing method provided by embodiments of the present disclosure includes acquiring, two adjacent frames of original images from a video image data stream; extracting a feature element that produces smear from the two adjacent frames of the original images; generating a reconstructed image frame that does not comprise the feature element by using the two adjacent frames of the original images and the feature element; and inserting the reconstructed image frame between the two adjacent frames of the original images.Type: ApplicationFiled: November 19, 2018Publication date: April 1, 2021Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Haifeng BI, Xin WANG, Yan FANG, Wenke LI, Yufeng BAO, Bailing LIU, Shun ZHAO, Lifeng CHEN
-
Patent number: 10930360Abstract: A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.Type: GrantFiled: January 8, 2019Date of Patent: February 23, 2021Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Peng Liu, Jun Fan, Yusheng Liu, Bailing Liu, Han Zhang, Zhen Wang, Yun Qiao, Zhengkui Wang, Lele Cong, Mei Li
-
Patent number: 10902930Abstract: A shift register includes a first input sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit. The first input sub-circuit is configured to transmit a voltage from the first signal terminal to the first node under control of the first voltage terminal. The pull-up control sub-circuit is configured to be in a turn-on or turn-off state under control of the first node. The pull-down control sub-circuit is configured to transmit a voltage from the third voltage terminal to the pull-down node under control of the first node, transmit the voltage from the third voltage terminal to the pull-down node under control of the signal output terminal, and transmit a voltage from the first clock signal terminal to the pull-down node under control of the first clock signal terminal.Type: GrantFiled: October 25, 2018Date of Patent: January 26, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng Liu, Zhen Wang, Han Zhang, Kai Zhang, Yun Qiao, Jian Sun, Bailing Liu, Fei Huang, Zhengkui Wang, Jianjun Zhang
-
Publication number: 20200005881Abstract: A shift register includes a first input sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit. The first input sub-circuit is configured to transmit a voltage from the first signal terminal to the first node under control of the first voltage terminal. The pull-up control sub-circuit is configured to be in a turn-on or turn-off state under control of the first node. The pull-down control sub-circuit is configured to transmit a voltage from the third voltage terminal to the pull-down node under control of the first node, transmit the voltage from the third voltage terminal to the pull-down node under control of the signal output terminal, and transmit a voltage from the first clock signal terminal to the pull-down node under control of the first clock signal terminal.Type: ApplicationFiled: October 25, 2018Publication date: January 2, 2020Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng LIU, Zhen WANG, Han ZHANG, Kai ZHANG, Yun QIAO, Jian SUN, Bailing LIU, Fei HUANG, Zhengkui WANG, Jianjun ZHANG
-
Publication number: 20190333597Abstract: A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.Type: ApplicationFiled: January 8, 2019Publication date: October 31, 2019Inventors: Peng LIU, Jun Fan, Yusheng Liu, Bailing Liu, Han Zhang, Zhen Wang, Yun Qiao, Zhengkui Wang, Lele Cong, Mei Li