Abstract: According to one aspect of the present disclosure, a memory device is provided. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The peripheral circuit is configured to receive a first instruction, in response to the first instruction, generate a dummy data and write the dummy data in the memory cell array, receive a second instruction indicating to perform a read operation in the memory cell array, and send a returned data based on the read operation. In response to a read data of the read operation comprising the dummy data, the returned data is set feature information indicating that the returned data comprises the dummy data.

Abstract: According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array. The memory device may include a peripheral circuit coupled to the memory cell array. The peripheral circuit may be configured to receive a first instruction indicating to write dummy data at a specified location in the memory cell array. The peripheral circuit may be configured to generate the dummy data to be written in response to the first instruction. The peripheral circuit may be configured to write the dummy data to be written at the specified location.

Abstract: According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array. The memory device may include a peripheral circuit coupled to the memory cell array. The peripheral circuit may be configured to receive a first instruction indicating to write dummy data at a specified location in the memory cell array. The peripheral circuit may be configured to generate the dummy data to be written in response to the first instruction. The peripheral circuit may be configured to write the dummy data to be written at the specified location.