Abstract: Embodiments disclose a package substrate. In an embodiment, the package substrate comprises a core, where the core comprises: a first sub-core, where the first sub-core comprises a glass and a first through glass via (TGV), and a second sub-core, where the second sub-core comprises the glass and a second TGV. In an embodiment, the first TGV directly contacts the second TGV.

Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a glass core with one or more openings with one or more dies placed in the opening such that the glass core surrounds the one or more dies. One or one or more through glass via filled with conductive material such as copper electrically couple a first side of the glass core with a second side of the glass core opposite the first side. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to dense integration of PICs in a substrate using an optical fanout structure that includes waveguides formed within a substrate to optically couple with the PICs at an edge of the substrate. One or more PICs may then be electrically with dies such as processor dies or memory dies. The one or more PICs may be located within a cavity in the substrate. The substrate may be made of glass or silicon. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.

Abstract: Semiconductor package substrates and methods of forming semiconductor package substrates are described. In an example, a semiconductor package substrate includes an interfacial layer between a metal layer and a dielectric layer. For example, the interfacial layer may be attached to the metal layer and the dielectric layer by a chemical bond, e.g., a coordinate bond or a covalent bond. Accordingly, the metal layer may adhere to the dielectric layer.

Abstract: Semiconductor package substrates and methods of forming semiconductor package substrates are described. In an example, a semiconductor package substrate includes an interfacial layer between a metal layer and a dielectric layer. For example, the interfacial layer may be attached to the metal layer and the dielectric layer by a chemical bond, e.g., a coordinate bond or a covalent bond. Accordingly, the metal layer may adhere to the dielectric layer.