Abstract: Disclosed is battery charging circuit having a first detection circuit and a second detection circuit for detecting when to terminate an activated voltage collapse protection operation. The first detection circuit may be an analog design and the second detection circuit may include digital circuitry.

Abstract: The described apparatus and methods may include a first shifting stage configured to receive a signal having an upper power rail at a first voltage level and a lower power rail at a second voltage level, the first shifting stage configured to shift the upper power rail from the first voltage level to a third voltage level while maintaining the lower power rail at the second voltage level. The apparatus and methods may also include a second shifting stage coupled to the first shifting stage and configured to shift the lower power rail from the second voltage level to a fourth voltage level while maintaining the upper power rail at the third voltage level, the second shifting stage further configured to transmit the signal having the upper power rail at the third voltage level and the lower power rail at the fourth voltage level.

Abstract: A battery monitoring circuit is described. The battery monitoring circuit includes a high counter that increments when a sense voltage measurement is above a threshold. The battery monitoring circuit also includes a low counter that increments when the sense voltage measurement is below the threshold. The battery monitoring circuit further includes state machine circuitry coupled to the high counter and to the low counter. The battery monitoring circuit additionally includes open circuit voltage monitoring circuitry coupled to the state machine circuitry. The battery monitoring circuit also includes resistance monitoring circuitry coupled to the state machine circuitry.

Abstract: A method and apparatus for providing a temperature sensing loop used in connection with a current sensing component, such as a BATFET, in order to compensate for variations in the BATFET's resistance due to temperature variations. The temperature sensing loop detects a temperature of the BATFET and regulates the gate voltage of the BATFET based on the detected temperature in order to compensate for changes in the BATFET's resistance. The temperature sensing feedback loop maintains the BATFET at a constant resistance for current sensing through negative feedback control. The BATFET and temperature sensing loop can be provided as components of an on-chip fuel gauging application for a UE.

Abstract: A method and apparatus that reduce common mode variations experienced by a voltage sensing component. A measurement component such as a BATFET or an external sensing resistor, receives, at its source, a voltage from the top of a battery having a voltage VPH_PWR. A voltage sensing component, such as an ADC, is powered by the voltage from the battery. A power referenced component, such as a power referenced LDO, tracks the voltage from the battery and outputs the tracked voltage minus a predetermined voltage amount to a negative side of the voltage sensing component.

Abstract: The described apparatus and methods may include a first shifting stage configured to receive a signal having an upper power rail at a first voltage level and a lower power rail at a second voltage level, the first shifting stage configured to shift the upper power rail from the first voltage level to a third voltage level while maintaining the lower power rail at the second voltage level. The apparatus and methods may also include a second shifting stage coupled to the first shifting stage and configured to shift the lower power rail from the second voltage level to a fourth voltage level while maintaining the upper power rail at the third voltage level, the second shifting stage further configured to transmit the signal having the upper power rail at the third voltage level and the lower power rail at the fourth voltage level.

Abstract: Disclosed is battery charging circuit having a first detection circuit and a second detection circuit for detecting when to terminate an activated voltage collapse protection operation. The first detection circuit may be an analog design and the second detection circuit may include digital circuitry.

Abstract: A method and apparatus for providing a temperature sensing loop used in connection with a current sensing component, such as a BATFET, in order to compensate for variations in the BATFET's resistance due to temperature variations. The temperature sensing loop detects a temperature of the BATFET and regulates the gate voltage of the BATFET based on the detected temperature in order to compensate for changes in the BATFET's resistance. The temperature sensing feedback loop maintains the BATFET at a constant resistance for current sensing through negative feedback control. The BATFET and temperature sensing loop can be provided as components of an on-chip fuel gauging application for a UE.

Abstract: A battery monitoring circuit is described. The battery monitoring circuit includes a high counter that increments when a sense voltage measurement is above a threshold. The battery monitoring circuit also includes a low counter that increments when the sense voltage measurement is below the threshold. The battery monitoring circuit further includes state machine circuitry coupled to the high counter and to the low counter. The battery monitoring circuit additionally includes open circuit voltage monitoring circuitry coupled to the state machine circuitry. The battery monitoring circuit also includes resistance monitoring circuitry coupled to the state machine circuitry.

Abstract: Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.

Abstract: Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.

Abstract: Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.

Abstract: Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.