Abstract: Disclosed are a method for chip packaging having a high-density connection layer and a chip packaging structure, the method comprising S1: preparing a high-density connection layer having multilayered metal wiring layer; S2: preparing a substrate intermediate, and attaching thereto the high-density connection layer; S3: embedding the high-density connection layer into the substrate and preparing a first type pads connected with the multilayered metal wiring layer and a second type pads connected with a wiring layer of the substrate intermediate; S4: inversely mounting the chip on the substrate surface, the first type chip bumps being connected to the first type pads, and the second type chip bumps being connected to the second type pads. Part of the wiring layer inside the substrate is replaced with single-sided or double-sided high-density connection layer to reduce the number of layers and thickness of the substrate, facilitating layout and wiring and improving integration and performance.

Abstract: Disclosed are a method for chip packaging having a high-density connection layer and a chip packaging structure, the method comprising S1: preparing a high-density connection layer having multilayered metal wiring layer; S2: preparing a substrate intermediate, and attaching thereto the high-density connection layer; S3: embedding the high-density connection layer into the substrate and preparing a first type pads connected with the multilayered metal wiring layer and a second type pads connected with a wiring layer of the substrate intermediate; S4: inversely mounting the chip on the substrate surface, the first type chip bumps being connected to the first type pads, and the second type chip bumps being connected to the second type pads. Part of the wiring layer inside the substrate is replaced with single-sided or double-sided high-density connection layer to reduce the number of layers and thickness of the substrate, facilitating layout and wiring and improving integration and performance.