Patents by Inventor Bala Padmakumar

Bala Padmakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8080871
    Abstract: One aspect of the invention includes a copper substrate; a catalyst on top of the copper substrate surface; and a thermal interface material that comprises a layer containing carbon nanotubes that contacts the catalyst. The carbon nanotubes are oriented substantially perpendicular to the surface of the copper substrate. A Raman spectrum of the layer containing carbon nanotubes has a D peak at ˜1350 cm?1 with an intensity ID, a G peak at ˜1585 cm?1 with an intensity IG, and an intensity ratio ID/IG of less than 0.7 at a laser excitation wavelength of 514 nm. The thermal interface material has: a bulk thermal resistance, a contact resistance at an interface between the thermal interface material and the copper substrate, and a contact resistance at an interface between the thermal interface material and a solid-state device. A summation of these resistances has a value of 0.06 cm2K/W or less.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Carlos Dangelo, Ephraim Suhir, Subrata Dey, Barbara Wacker, Yuan Xu, Arthur Boren, Darin Olsen, Yi Zhang, Peter Schwartz, Bala Padmakumar
  • Publication number: 20110103020
    Abstract: One aspect of the invention includes a copper substrate; a catalyst on top of the copper substrate surface; and a thermal interface material that comprises a layer containing carbon nanotubes that contacts the catalyst. The carbon nanotubes are oriented substantially perpendicular to the surface of the copper substrate. A Raman spectrum of the layer containing carbon nanotubes has a D peak at ˜1350 cm?1 with an intensity ID, a G peak at ˜1585 cm?1 with an intensity IG, and an intensity ratio ID/IG of less than 0.7 at a laser excitation wavelength of 514 nm. The thermal interface material has: a bulk thermal resistance, a contact resistance at an interface between the thermal interface material and the copper substrate, and a contact resistance at an interface between the thermal interface material and a solid-state device. A summation of these resistances has a value of 0.06 cm2K/W or less.
    Type: Application
    Filed: July 22, 2008
    Publication date: May 5, 2011
    Inventors: Carlos Dangelo, Ephraim Suhir, Subrata Dey, Barbara Wacker, Yuan Xu, Arthur Boren, Darin Olsen, Yi Zhang, Peter Schwartz, Bala Padmakumar
  • Patent number: 7656027
    Abstract: An in-chip system and method for removing heat from integrated circuits is disclosed. One embodiment is a substrate with a front side and a back side. The front side of the substrate is capable of having formed thereon a plurality of transistors. A plurality of structures within the substrate contain a solid heat conductive media comprising carbon nanotubes and/or a metal, such as copper. At least some of the plurality of structures extend from the back side of the substrate into the substrate. In some embodiments, the carbon nanotubes are formed within the substrate using a catalyst.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: February 2, 2010
    Assignee: Nanoconduction, Inc.
    Inventors: Carlos Dangelo, Bala Padmakumar
  • Publication number: 20060278901
    Abstract: An in-chip system and method for removing heat from integrated circuits is disclosed. One embodiment is a substrate with a front side and a back side. The front side of the substrate is capable of having formed thereon a plurality of transistors. A plurality of structures within the substrate contain a solid heat conductive media comprising carbon nanotubes and/or a metal, such as copper. At least some of the plurality of structures extend from the back side of the substrate into the substrate. In some embodiments, the carbon nanotubes are formed within the substrate using a catalyst.
    Type: Application
    Filed: May 30, 2006
    Publication date: December 14, 2006
    Inventors: Carlos Dangelo, Bala Padmakumar
  • Patent number: 4986878
    Abstract: A method of manufacturing an integrated circuit having a multilayer structure where the method includes the steps of depositing a thin layer of low temperature oxide (LTO) on top of conductors and then spinning and curing a thin layer of spin-on-glass to planarize the surface of the device. This structure is then plasma etched to remove the spin-on-glass and a portion of the LTO at approximately the same rate. The structure is then dipped in a mild potassium hydroxide solution to completely remove the SOG material, even from the crevices and gaps which are present on the surface. This enables the device to be manufactured free of any organic substances from the SOG in the body of the structure. A passivation layer can now be deposited to protect the underlying circuitry from ionic contamination, water vapor penetration and handling.
    Type: Grant
    Filed: July 19, 1988
    Date of Patent: January 22, 1991
    Assignee: Cypress Semiconductor Corp.
    Inventors: Alp Malazgirt, Bala Padmakumar, Arya Bhattacherjee