Patents by Inventor BALAJI BAPU GURURAJA RAO
BALAJI BAPU GURURAJA RAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11755475Abstract: An information handling system includes first and second memory modules, and a central processing unit. The first memory module includes one or more memory ranks of memory devices, and a first plurality of thermal sensors. The second memory module includes one or more memory ranks of memory devices, and a second plurality of thermal sensors. The central processing unit receives first thermal telemetry data for the first memory module from the first thermal sensors, and second thermal telemetry data for the second memory module from the second thermal sensors. In response to the reception of the first thermal telemetry data, the central processing unit determines a first localized temperature of a first memory rank. In response to the first localized temperature exceeding a threshold temperature, the central processing unit re-maps access of data from the first memory rank to a second memory rank.Type: GrantFiled: January 31, 2020Date of Patent: September 12, 2023Assignee: Dell Products L.P.Inventors: Balaji Bapu Gururaja Rao, Jordan Chin, Stuart Allen Berke
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Patent number: 11409883Abstract: An information handling system may include a circuit board; a processor disposed on the circuit board, wherein the processor includes a media access control (MAC) address and a hidden root key (HRK) encoded therein; and a memory not disposed on the circuit board. The information handling system may be configured to: determine a customer public key (CPK); create a data structure comprising the CPK and the MAC address; encrypt the data structure using the HRK to generate an encrypted structure; and store the encrypted structure in the memory.Type: GrantFiled: January 19, 2021Date of Patent: August 9, 2022Assignee: Dell Products L.P.Inventors: Balaji Bapu Gururaja Rao, Elie Jreij, Paul Vancil, Marshal Savage
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Publication number: 20220229911Abstract: An information handling system may include a circuit board; a processor disposed on the circuit board, wherein the processor includes a media access control (MAC) address and a hidden root key (HRK) encoded therein; and a memory not disposed on the circuit board. The information handling system may be configured to: determine a customer public key (CPK); create a data structure comprising the CPK and the MAC address; encrypt the data structure using the HRK to generate an encrypted structure; and store the encrypted structure in the memory.Type: ApplicationFiled: January 19, 2021Publication date: July 21, 2022Applicant: Dell Products L.P.Inventors: Balaji Bapu Gururaja RAO, Elie JREIJ, Paul VANCIL, Marshal SAVAGE
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Patent number: 11194377Abstract: An information handling system includes a processor, a graphics processing unit (GPU), and a baseboard management controller (BMC). The BMC includes a power ratio table with a plurality of entries, each correlating a workload with a power ratio of a power level of the processor when the particular workload is instantiated on the information handing system to a power level of the GPU when the particular workload is instantiated on the information handling system. The BMC determines that the power ratio table includes an entry associated with a workload instantiated on the information handling system, determines that a total power level of the information handling system is greater than a power level threshold, and throttles a power level of the processor and a power level of the GPU based upon a power ratio of the entry in response to determining that the total power level is greater than the power level threshold.Type: GrantFiled: January 21, 2020Date of Patent: December 7, 2021Assignee: Dell Products L.P.Inventors: Balaji Bapu Gururaja Rao, Elie Antoun Jreij, John Erven Jenne
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Publication number: 20210365301Abstract: A disaggregated information handling system includes processing sleds and an abstraction layer module. Each processing sled includes disaggregated processing elements. The abstraction layer module may discover the processing elements, determine an availability score for each of the processing elements, receive an allocation request for an allocation of at least one of the processing elements, and allocate a first one of the processing elements based upon the first processing element having a highest availability score.Type: ApplicationFiled: May 21, 2020Publication date: November 25, 2021Inventors: Balaji Bapu Gururaja Rao, John Erven Jenne, Elie Antoun Jreij, Shekar Babu Suryanarayana
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Patent number: 11171788Abstract: A converged infrastructure includes a shared device and compute devices. The compute devices include a baseboard management controller and applications including one or more entitled initiators. The baseboard management controllers generate a distributed provision list including certificates chains for the entitled initiators; and configure the shared device with the certificate chains. The shared device receive a critical command and an encrypted hash, determine a calculated hash of the critical command, decrypt the encrypted hash using keys from the certificate chains, and compare the calculated hash with the decrypted hashes to determine if the critical command comes from one of the entitled initiators.Type: GrantFiled: June 3, 2019Date of Patent: November 9, 2021Assignee: Dell Products L.P.Inventors: Balaji Bapu Gururaja Rao, Cyril Jose, Chandrashekar Nelogal, Akshata Sheshagiri Naik
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Patent number: 11153320Abstract: Methods, systems, and computer programs encoded on computer storage medium, for identifying a first user access event that failed authentication at the first computing device; creating a transaction block of a distributed ledger based on the first user access event; determining that data indicating the first user access event is not included by the distributed ledger, and in response, adding the transaction block to a temporal vector space of the distributed ledger; sharing, to each other computing device of the local network, the transaction block, wherein each of the others computing devices of the local network updates a local copy of the distributed ledger to include the transaction block in the temporal vector space.Type: GrantFiled: February 15, 2019Date of Patent: October 19, 2021Assignee: DELL PRODUCTS L.P.Inventors: Cyril Jose, Balaji Bapu Gururaja Rao, Akshata Sheshagiri Naik, Yogesh Prabhakar Kulkarni
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Publication number: 20210240617Abstract: An information handling system includes first and second memory modules, and a central processing unit. The first memory module includes one or more memory ranks of memory devices, and a first plurality of thermal sensors. The second memory module includes one or more memory ranks of memory devices, and a second plurality of thermal sensors. The central processing unit receives first thermal telemetry data for the first memory module from the first thermal sensors, and second thermal telemetry data for the second memory module from the second thermal sensors. In response to the reception of the first thermal telemetry data, the central processing unit determines a first localized temperature of a first memory rank. In response to the first localized temperature exceeding a threshold temperature, the central processing unit re-maps access of data from the first memory rank to a second memory rank.Type: ApplicationFiled: January 31, 2020Publication date: August 5, 2021Inventors: Balaji Bapu Gururaja Rao, Jordan Chin, Stuart Allen Berke
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Publication number: 20210223848Abstract: An information handling system includes a processor, a graphics processing unit (GPU), and a baseboard management controller (BMC). The BMC includes a power ratio table with a plurality of entries, each correlating a workload with a power ratio of a power level of the processor when the particular workload is instantiated on the information handing system to a power level of the GPU when the particular workload is instantiated on the information handling system. The BMC determines that the power ratio table includes an entry associated with a workload instantiated on the information handling system, determines that a total power level of the information handling system is greater than a power level threshold, and throttles a power level of the processor and a power level of the GPU based upon a power ratio of the entry in response to determining that the total power level is greater than the power level threshold.Type: ApplicationFiled: January 21, 2020Publication date: July 22, 2021Inventors: Balaji Bapu Gururaja Rao, Elie Antoun Jreij, John Erven Jenne
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Publication number: 20210208650Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a power supply unit for supplying electrical energy to information handling resources of the information handling system, a battery backup unit for supplying electrical energy to the information handling resources responsive to a power event associated with the power supply unit, and a non-transitory computer-readable readable medium having embodied thereon a program of instructions configured to, when executed, in response to the power event, gracefully terminate one or more applications executing on the processor in accordance with a desired priority ranking.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Applicant: DELL PRODUCTS L.P.Inventors: Dinesh Kunnathur Ragupathi, Yogesh Prabhakar Kulkarni, Balaji Bapu Gururaja Rao, Elie Antoun Jreij, Pushkala Iyer
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Patent number: 10955886Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a power supply unit for supplying electrical energy to information handling resources of the information handling system, a battery backup unit for supplying electrical energy to the information handling resources responsive to a power event associated with the power supply unit, and a non-transitory computer-readable readable medium having embodied thereon a program of instructions configured to, when executed, in response to the power event, gracefully terminate one or more applications executing on the processor in accordance with a desired priority ranking.Type: GrantFiled: May 12, 2016Date of Patent: March 23, 2021Assignee: DELL PRODUCTS L.P.Inventors: Dinesh Kunnathur Ragupathi, Yogesh Prabhakar Kulkarni, Balaji Bapu Gururaja Rao, Elie Antoun Jreij, Pushkala Iyer
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Patent number: 10877553Abstract: A system may include a rack, a rack manager, and a block controller. The rack manager may be configured to communicatively couple to each of respective baseboard management controllers of information handling systems of the rack and also configured to manage power consumption by information handling resources housed in the rack. The block controller may be configured to monitor and report information regarding power consumption by the plurality of storage resources to the at least one of the baseboard management controllers, the at least one of the baseboard management controllers may be configured to communicate the information regarding power consumption by the plurality of storage resources to the rack manager, and the rack manager may be configured to manage power consumption by information handling resources housed in the rack based on the information regarding power consumption by the plurality of storage resources.Type: GrantFiled: April 13, 2018Date of Patent: December 29, 2020Assignee: Dell Products L.P.Inventors: Chandrasekhar Mugunda, Yogesh P. Kulkarni, Balaji Bapu Gururaja Rao, Rui An
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Publication number: 20200382312Abstract: A converged infrastructure includes a shared device and compute devices. The compute devices include a baseboard management controller and applications including one or more entitled initiators. The baseboard management controllers generate a distributed provision list including certificates chains for the entitled initiators; and configure the shared device with the certificate chains. The shared device receive a critical command and an encrypted hash, determine a calculated hash of the critical command, decrypt the encrypted hash using keys from the certificate chains, and compare the calculated hash with the decrypted hashes to determine if the critical command comes from one of the entitled initiators.Type: ApplicationFiled: June 3, 2019Publication date: December 3, 2020Inventors: Balaji Bapu Gururaja Rao, Cyril Jose, Chandrashekar Nelogal, Akshata Sheshagiri Naik
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Patent number: 10846183Abstract: An information handling system includes a persistent storage and a memory controller. The persistent storage includes a volatile memory and a non-volatile memory. The memory controller stores data and metadata for a data file within the volatile memory, and the data file is synchronized within other information handling systems of a storage cluster. The memory controller updates the metadata in response to a change in the data of the data file, stores the data and the metadata for the data file within the non-volatile memory prior to a power loss of the information handling system, and synchronizes the data and the metadata of the data file with current data and current metadata for the data file found in the other information handling systems in response to the information handling system being back online. The data is synchronized with the current metadata based on a transform for the data file being received from the other information handling systems.Type: GrantFiled: June 11, 2018Date of Patent: November 24, 2020Inventors: Balaji Bapu Gururaja Rao, Syama S. Poluri, Chandrashekar Nelogal
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Patent number: 10782993Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a memory subsystem and a processor subsystem communicatively coupled to the memory subsystem and configured to execute a hypervisor, wherein the hypervisor is configured to host a plurality of virtual machines and host an interface to the memory subsystem, wherein the interface is configured to dynamically modify sizes of namespaces instantiated within the memory subsystem by maintaining super metadata associated with each of a plurality of memory modules of the memory subsystem, wherein the super metadata for a particular memory module of the memory subsystem includes one or more entries for the particular memory module, each entry defining a namespace of the particular memory module and recording an offset of the latest written data in the namespace.Type: GrantFiled: October 13, 2017Date of Patent: September 22, 2020Assignee: Dell Products L.P.Inventors: Balaji Bapu Gururaja Rao, Shekar Babu Suryanarayana, Yogesh P. Kulkarni
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Publication number: 20200267158Abstract: Methods, systems, and computer programs encoded on computer storage medium, for identifying a first user access event that failed authentication at the first computing device; creating a transaction block of a distributed ledger based on the first user access event; determining that data indicating the first user access event is not included by the distributed ledger, and in response, adding the transaction block to a temporal vector space of the distributed ledger; sharing, to each other computing device of the local network, the transaction block, wherein each of the others computing devices of the local network updates a local copy of the distributed ledger to include the transaction block in the temporal vector space.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Cyril Jose, Balaji Bapu Gururaja Rao, Akshata Sheshagiri Naik, Yogesh Prabhakar Kulkarni
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Patent number: 10732859Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory system communicatively coupled to the processor. The memory system may include one or more persistent memory modules, each of the one or more persistent memory modules comprising a volatile memory and a non-volatile memory and one or more health registers accessible to a host system executing on the processor, the health registers storing health information indicating, for each of a plurality of ranks of the volatile memory, whether the memory system can reliably perform a save operation to a portion of non-volatile memory mapped to volatile memory of the rank.Type: GrantFiled: October 6, 2017Date of Patent: August 4, 2020Assignee: Dell Products L.P.Inventors: Vadhiraj Sankaranarayanan, Krishna Pradyumna Kakarla, Balaji Bapu Gururaja Rao, Elie Antoun Jreij
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Patent number: 10725767Abstract: A system for ensuring update package authenticity includes an update package transaction ledger and a repository. Change managers are configured to maintain the update package transaction ledger, create a transaction block using metadata of an update, and determine a package value based on the transaction ledger and on the update. The change managers also incorporate the package value and the update into a package, and upload the package to the repository. A client obtains the package from the repository, obtains the transaction block from the update package transaction ledger, determines a calculated value based on the transaction block and on the update, and compares the calculated value and the package value. The update is installed when the calculated value and the package value match.Type: GrantFiled: October 15, 2018Date of Patent: July 28, 2020Assignee: Dell Products, L.P.Inventors: Cyril Jose, Akshata Sheshagiri Naik, Balaji Bapu Gururaja Rao, Raveendra Babu Madala
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Patent number: 10728086Abstract: A server rack may include a chassis controller for the server rack and a set of baseboard management controllers (BMCs) corresponding to servers stored in the server rack. Each BMC is communicatively connected to the chassis controller internal to the server rack. Each BMC is also communicatively connected to a network switch located external to the server rack to communicate with the set of BMCs using the network switch. When a first BMC loses communication with the chassis controller internal to the server rack, the first BMC communicates with the chassis controller via a second BMC and the network switch.Type: GrantFiled: March 23, 2017Date of Patent: July 28, 2020Assignee: Dell Products, L.P.Inventors: Balaji Bapu Gururaja Rao, Elie A. Jreij, Pushkala Iyer, Cyril Jose
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Patent number: 10678467Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a persistent memory system communicatively coupled to the processor, the persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of how save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system.Type: GrantFiled: October 6, 2017Date of Patent: June 9, 2020Assignee: Dell Products L.P.Inventors: Vadhiraj Sankaranarayanan, Krishna Pradyumna Kakarla, Balaji Bapu Gururaja Rao, Elie Antoun Jreij