Patents by Inventor Balaji Krishnakumar

Balaji Krishnakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12117882
    Abstract: A system having: a processor, wherein the processor is configured for executing a process of reducing power consumption that includes executing a first task over a first plurality of timeslots and a second task over a second plurality of timeslots, and wherein the processor is configured to: execute a real-time operating system (RTOS) process; determine that the first task is complete during a first timeslot of the first plurality of timeslots; and enter a low power mode for a reminder of the first timeslot upon determining that there is enough time to enter a low power mode during the first timeslot and a next timeslot is allocated to the first task, otherwise perform a dead-wait for the reminder of the first timeslot.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: October 15, 2024
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Balaji Krishnakumar
  • Publication number: 20240241563
    Abstract: A system having: a processor, wherein the processor is configured for executing a process of reducing power consumption that includes executing a first task over a first plurality of timeslots and a second task over a second plurality of timeslots, and wherein the processor is configured to: execute a real-time operating system (RTOS) process; determine that the first task is complete during a first timeslot of the first plurality of timeslots; and enter a low power mode for a reminder of the first timeslot upon determining that there is enough time to enter a low power mode during the first timeslot and a next timeslot is allocated to the first task, otherwise perform a dead-wait for the reminder of the first timeslot.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 18, 2024
    Inventor: Balaji Krishnakumar
  • Publication number: 20180173622
    Abstract: A method and system to perform deterministic timing analysis of a plurality of software tasks involves cache memory that is shared by the plurality of software tasks. Real memory is accessible by the plurality of software tasks. A task scheduler establishes a cache flush between executions of consecutive tasks among the plurality of software tasks. The cache flush includes movement of data in the cache memory to the real memory. A processor executes the plurality of software tasks to obtain a worst case execution time (WCET) associated with each of the plurality of software tasks.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Brian Fruechtenicht, Terrence R. Leibham, Alex Pereira, Jeffery S. Schmidt, Balaji Krishnakumar