Patents by Inventor Balaji Krishnamachary

Balaji Krishnamachary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230297930
    Abstract: Embodiments of the present disclosure relates to a method and a business intelligence system for building actionable knowledge based intelligent enterprise system. The present disclosure proposes a solution which considers atomic executable process and its data as digital twins. Further, a triangulated integration of a plurality of digital twins is performed for identifying inter-process and intra-process correlation between the atomic executable process and its data. The correlation provides insights of business knowledge and helps in determining actionable business intelligence. The actionable business intelligence transforms the enterprise system into an intelligent enterprise system.
    Type: Application
    Filed: March 31, 2022
    Publication date: September 21, 2023
    Inventor: BALAJI KRISHNAMACHARY IYENGAR
  • Publication number: 20180200194
    Abstract: The present invention relates to compositions and methods for disrupting cancer stromal cell networks using synthetic nanoparticles coated with plasma membranes.
    Type: Application
    Filed: August 12, 2016
    Publication date: July 19, 2018
    Inventors: Zaver M. Bhujwalla, Jiefu Jin, Sridhar Nimmagadda, Balaji Krishnamachary
  • Patent number: 5490095
    Abstract: In extracting parameters for use in circuit simulation of an IC device having a plurality of insulated gate field-effect transistors (IGFETs), layout data for patterns for the IC device are prepared. The patterns include gate patterns for the IGFETs, at least one of which is a bent gate pattern such that drain and source regions are defined on opposite sides of the bent gate pattern. An index symbol data is added to the layout data, which is for the bent gate pattern, to thereby form designed pattern data. For higher accuracy of the circuit simulation, the index symbol data in the designed pattern data is detected and used to produce parameters concerning the gate patterns for the IGFETs, thereby contributing to determination of a capability of controlling electric current in the IGFETs.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: February 6, 1996
    Assignees: Hitachi, Ltd., VLSI Technology Incorporated
    Inventors: Shigeru Shimada, Michael Saniei, Balaji Krishnamachary
  • Patent number: 5461579
    Abstract: A method estimates source resistance for a transistor. A substrate region under a gate for the transistor is modeled as a gate region having a uniform resistivity .rho..sub.g. A source of the transistor is modeled as a source region having a uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s1 are used to calculate a first current from the source of the transistor to a drain of the transistor. The source of the transistor is then modeled as a source region having another uniform resistivity .rho..sub.s2. The uniform resistivity .rho..sub.s2, is different in value than uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s2 are used to calculate a second current from the source of the transistor to a drain of the transistor. The uniform resistivity .rho..sub.s1, the uniform resistivity .rho..sub.
    Type: Grant
    Filed: May 11, 1994
    Date of Patent: October 24, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Michael N. Misheloff, Balaji Krishnamachary, Osman E. Akcasu