Patents by Inventor Balaji Narendran Chellappa

Balaji Narendran Chellappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825642
    Abstract: A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 21, 2017
    Assignee: NVIDIA Corporation
    Inventors: Balaji Narendran Chellappa, Paul Aymeric Fontaine
  • Publication number: 20160352348
    Abstract: A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 1, 2016
    Inventors: Balaji NARENDRAN CHELLAPPA, Paul Aymeric FONTAINE
  • Patent number: 9419638
    Abstract: A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: August 16, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Balaji Narendran Chellappa, Paul Aymeric Fontaine
  • Patent number: 9065413
    Abstract: An apparatus comprises a selected volume detector that detects a selected output volume; an analog output signal amplifier; a digital volume amplifier; a boost gain control element coupled to the selected volume detector; the analog output signal amplifier; and the digital volume amplifier; wherein the boost gain control element is configured to: keep a gain of a path of the digital volume amplifier and the analog output signal amplifier substantially constant, wherein the boost gain control element can adjust both: a) a gain of the digital volume control; and b) a gain of the analog output signal amplifier; to keep the gain of the path of the digital volume amplifier and the analog output signal substantially constant and equal to the selected output volume.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: June 23, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Angelo William Pereira, Paul-Herve Aymeric Fontaine, Michel Vercier, Chintan Trehan, Sooping Saw, Balaji Narendran Chellappa
  • Publication number: 20130188808
    Abstract: An apparatus comprises a selected volume detector that detects a selected output volume; an analog output signal amplifier; a digital volume amplifier; a boost gain control element coupled to the selected volume detector; the analog output signal amplifier; and the digital volume amplifier; wherein the boost gain control element is configured to: keep a gain of a path of the digital volume amplifier and the analog output signal amplifier substantially constant, wherein the boost gain control element can adjust both: a) a gain of the digital volume control; and b) a gain of the analog output signal amplifier; to keep the gain of the path of the digital volume amplifier and the analog output signal substantially constant and equal to the selected output volume.
    Type: Application
    Filed: April 10, 2012
    Publication date: July 25, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Angelo William Pereira, Paul-Herve Aymeric Fontaine, Michel Vercier, Chintan Trehan, Sooping Saw, Balaji Narendran Chellappa