Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.

Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.

Abstract: A connection apparatus has a USB port coupled to a USB interface for connection to a computing device enabled to manage IP audio calls, a land-line telephone port coupled to a Four-Wire Analog telephone interface, for connection to a Four-Wire port of a land-line telephone, a wireless interface for coupling to a communication device enabled to manage voice calls over a network, an analog audio port for a headset, coupled to an analog audio interface, a plurality of protocol translation modules, and switching circuitry enabled to connecting individual ones of the ports through individual ones of the protocol translation modules.

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

Abstract: A variable capacitance semiconductor structure is disclosed. Embodiments include a capacitor having three plates, a top plate, a middle plate, and a bottom plate. The top plate serves as a positive plate. The middle and bottom plates serve as ground plates for the capacitor. A switching circuit selects between the middle plate and the bottom plate for use as the ground plate of the capacitor. The middle plate is slotted, allowing electric fields to penetrate through the middle plate to the bottom plate. The slots prevent the electric fields from terminating at the middle plate. A different capacitance value can be selected, depending on whether the middle plate or bottom plate is selected as the ground plate. Logic circuitry is configured to control the selection of plates to achieve a variety of capacitance values.

Abstract: A variable capacitance semiconductor structure is disclosed. Embodiments include a capacitor having three plates, a top plate, a middle plate, and a bottom plate. The top plate serves as a positive plate. The middle and bottom plates serve as ground plates for the capacitor. A switching circuit selects between the middle plate and the bottom plate for use as the ground plate of the capacitor. The middle plate is slotted, allowing electric fields to penetrate through the middle plate to the bottom plate. The slots prevent the electric fields from terminating at the middle plate. A different capacitance value can be selected, depending on whether the middle plate or bottom plate is selected as the ground plate. Logic circuitry is configured to control the selection of plates to achieve a variety of capacitance values.

Abstract: A connection apparatus has a USB port coupled to a USB interface for connection to a computing device enabled to manage IP audio calls, a land-line telephone port coupled to a Four-Wire Analog telephone interface, for connection to a Four-Wire port of a land-line telephone, a wireless interface for coupling to a communication device enabled to manage voice calls over a network, an analog audio port for a headset, coupled to an analog audio interface, a plurality of protocol translation modules, and switching circuitry enabled to connecting individual ones of the ports through individual ones of the protocol translation modules.

Abstract: Apparatus, systems, and methods may operate to construct a file system tree that includes files to be accessed according to a plurality of custom access control list (ACL) access mechanisms registered by a corresponding plurality of applications, or a default ACL access mechanism. To access the files, metadata can be read/written using a multiple protocol file system cache engine and one of the ACL access mechanisms. In some embodiments, operations may include registering, in response to a request by an application, a selected one of the plurality of custom ACL access mechanisms with a library coupled to a multiple protocol file system cache engine. Further operations may include accessing a file system through the multiple protocol file system cache engine using the selected one of the plurality of custom ACL access mechanisms, or a default ACL access mechanism. Additional apparatus, systems, and methods are disclosed.

Abstract: There is disclosed a system and method for allocation of mainframe computing resources using distributed computing. In particular, the present application is directed to a system whereby a mainframe process intended for execution on a metered processor may be identified as executable on a non-metered processor. Thereafter, the mainframe computer may initiate execution of the remote process on the remote non-metered processor. If necessary, high-speed access to data available to the metered processor is provided to the non-metered processor. The process operates directly on data available to the metered processor. Once completed, the process signals the mainframe computer that the process is complete. Both metered and non-metered processor configuration and management may be accomplished using the administrative interface.

Abstract: Apparatus, systems, and methods may operate to construct a file system tree that includes files to be accessed according to a plurality of custom access control list (ACL) access mechanisms registered by a corresponding plurality of applications, or a default ACL access mechanism. To access the files, metadata can be read/written using a multiple protocol file system cache engine and one of the ACL access mechanisms. In some embodiments, operations may include registering, in response to a request by an application, a selected one of the plurality of custom ACL access mechanisms with a library coupled to a multiple protocol file system cache engine. Further operations may include accessing a file system through the multiple protocol file system cache engine using the selected one of the plurality of custom ACL access mechanisms, or a default ACL access mechanism. Additional apparatus, systems, and methods are disclosed.

Abstract: A process is provided for doping both sidewalls (26, 28) of isolation trenches (24, 26, 28) and connector regions (46, 48) between sources (58) and gate areas (62) and between drains (60) and gate areas in silicon CMOS devices. Appropriately doped glasses (16, 18, 30) formed on the silicon substrate (14) serve as the source of doping.

Abstract: A method for forming doped, conductive plugs to fill and planarize contact windows in integrated circuits is disclosed. The process is applicable to CMOS, NMOS and bipolar technologies. Discrete, sized, contact apertures formed superposing junction regions of a substrate are filled with semiconductor material and the semiconductor material is doped to match the conductivity type of the underlying junction regions. Thus, the integrated circuit structure is substantially planarized for formation of interconnect layers.