Abstract: A silicon sensor device includes: a plurality of metal layers; and a plurality of dielectric layers. Each of the plurality of metal layers is disposed on a respective dielectric layer, and wherein each of the plurality of metal layers is separated from an adjacent metal layer by a respective dielectric layer. The plurality of metal layers include: a first metal layer comprising a plurality of transmitter electrodes and a plurality of receiver electrodes; a second metal layer disposed beneath the first metal layer, wherein the second metal layer comprises a plurality of routing traces for the plurality of transmitter electrodes and a plurality of shielding blocks; and one or more circuit layers disposed beneath the second metal layer. A respective shielding block of the plurality of shielding blocks is configured to shield a respective portion of a respective receiver electrode of the plurality of receiver electrodes.

Abstract: A silicon sensor device includes: a plurality of metal layers; and a plurality of dielectric layers. Each of the plurality of metal layers is disposed on a respective dielectric layer, and wherein each of the plurality of metal layers is separated from an adjacent metal layer by a respective dielectric layer. The plurality of metal layers include: a first metal layer comprising a plurality of transmitter electrodes and a plurality of receiver electrodes; a second metal layer disposed beneath the first metal layer, wherein the second metal layer comprises a plurality of routing traces for the plurality of transmitter electrodes and a plurality of shielding blocks; and one or more circuit layers disposed beneath the second metal layer. A respective shielding block of the plurality of shielding blocks is configured to shield a respective portion of a respective receiver electrode of the plurality of receiver electrodes.

Abstract: A circuit includes a controller circuit configured to receive an output voltage of a converter and adjust a switching frequency of the converter in response to a status of an output load and an output load sensing circuit configured to determine the status of the output load and provide the peak current to the controller circuit. The output load sensing circuit may include a first timer configured to provide a delayed first signal to a peak current control in response to the output load being a heavy load. A second timer may be configured to provide a delayed second signal to the peak current control in response to the output load being a light load. The peak current control may be configured to adjust a peak current based on the received first signal and the second signal and configured to provide the peak current to the controller circuit.

Abstract: A circuit includes a controller circuit configured to receive an output voltage of a converter and adjust a switching frequency of the converter in response to a status of an output load and an output load sensing circuit configured to determine the status of the output load and provide the peak current to the controller circuit. The output load sensing circuit may include a first timer configured to provide a delayed first signal to a peak current control in response to the output load being a heavy load. A second timer may be configured to provide a delayed second signal to the peak current control in response to the output load being a light load. The peak current control may be configured to adjust a peak current based on the received first signal and the second signal and configured to provide the peak current to the controller circuit.

Abstract: Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.

Abstract: Systems and methods are provided for improved stability of driver amplifiers. In one example, a system includes an NMOSFET power device operable to generate a current signal at a drain terminal. The system further includes a current comparison amplifier operable to amplify a difference signal comprising a difference between a replica current signal of the NMOSFET power device and a reference current signal to drive a current comparison amplifier voltage output signal. The system further includes a PMOSFET clamp device comprising a source terminal coupled to a gate terminal of the NMOSFET power device operable to limit a voltage at the gate terminal of the NMOSFET power device responsive to the current comparison amplifier voltage output signal.

Abstract: Systems and methods are provided for improved noise performance of audio amplifiers. In one example, a system includes a multistage amplifier comprising at least a first stage amplifier and a second stage amplifier. The system further includes a plurality of switches disposed within the multistage amplifier to configure the multistage amplifier. The system further includes a control signal configured to control the multistage amplifier to a normal amplification mode or a mute state, wherein the multistage amplifier is adapted to amplify an input signal in the normal amplification mode, the multistage amplifier is adapted to output a zero signal in the mute state, and internal amplification stages of the multistage amplifier are disabled in the mute state, and output stages of each of the at least first stage amplifier and the second stage amplifier are electrically shorted and/or shorted to a fixed bias voltage in the mute state.

Abstract: Systems and methods according to one or more embodiments provide a low power current steering digital-to-analog converter. In one example, a device includes a current cell including a plurality of switches. The device further includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state before the current cell receives the first data signal. Related systems and methods are also provided.

Abstract: Systems and methods according to one or more embodiments provide a low power current steering digital-to-analog converter. In one example, a device includes a current cell including a plurality of switches. The device further includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state before the current cell receives the first data signal. Related systems and methods are also provided.

Abstract: Systems and methods are provided for improved noise performance of audio amplifiers. In one example, a system includes a multistage amplifier comprising at least a first stage amplifier and a second stage amplifier. The system further includes a plurality of switches disposed within the multistage amplifier to configure the multistage amplifier. The system further includes a control signal configured to control the multistage amplifier to a normal amplification mode or a mute state, wherein the multistage amplifier is adapted to amplify an input signal in the normal amplification mode, the multistage amplifier is adapted to output a zero signal in the mute state, and internal amplification stages of the multistage amplifier are disabled in the mute state, and output stages of each of the at least first stage amplifier and the second stage amplifier are electrically shorted and/or shorted to a fixed bias voltage in the mute state.

Abstract: Systems and methods are provided for improved stability of driver amplifiers. In one example, a system includes an NMOSFET power device operable to generate a current signal at a drain terminal. The system further includes a current comparison amplifier operable to amplify a difference signal comprising a difference between a replica current signal of the NMOSFET power device and a reference current signal to drive a current comparison amplifier voltage output signal. The system further includes a PMOSFET clamp device comprising a source terminal coupled to a gate terminal of the NMOSFET power device operable to limit a voltage at the gate terminal of the NMOSFET power device responsive to the current comparison amplifier voltage output signal.

Abstract: Systems and methods are provided for improved stability of audio amplifiers that incorporate external speaker connectivity. In one example, a system includes an audio amplifier circuit comprising two or more amplifier stages and a stability resistor and configured to receive an audio input signal, the audio amplifier circuit configured for at least two modes of operation, a first mode having a high input transconductance and the stability resistor is coupled to an output of the audio amplifier circuit, and a second mode having a lower input transconductance and the stability resistor is decoupled from the output of the audio amplifier circuit. The system further includes an amplitude detection circuit configured to provide a signal mode detection signal, an amplifier switching circuit configured to adjust a variable input transconductance of at least one of the amplifier stages, and a load switching circuit configured to couple and decouple the stability resistor at the output of the audio amplifier circuit.