Abstract: A cloud broker and procurement system and method is closed. In particular embodiments, the method includes receiving an offer of a computing resource from each of a plurality of providers. The method further includes receiving, from each of the plurality of providers, a service level agreement associated with each respective offered computing resource. Additionally, the method includes normalizing each of the service level agreements associated with the offered computing resources. The method further includes receiving a request from a requesting computer for a computing resource and selecting, based at least in part on the normalized service level agreements, one of the providers to provide the requested computing resource. The method also includes transmitting a service match indicator to the client, wherein the service match indicator indicates a time at which the offered computing resource will be utilized, and utilizing the computing resource on the selected provider.

Abstract: Order indication logic can be recycled for at least two different data hazards, thus reducing the amount of processor real estate consumed by data hazard resolution logic. The logic also allows a single priority picker to be utilized for coloring without the cost of additional pipeline stages. A single priority picker can be utilized to identify memory operations for performing RAW bypass and for resolving OERs. For instance, a data hazard resolution unit resolves at least two different data hazards between resident memory operations and incoming memory operations with a set of logic that indicates order of the resident memory operations relative to the incoming memory operations. The indicated order corresponds to the data hazard being resolved. The data hazard resolution unit includes a priority picker to select one of the indicated resident memory operations for either data hazard.

Abstract: It has been discovered that preventing performance of ineffective write operations reduces demand on memory bandwidth, as well as preventing unnecessary consumption of resources. A write operation is inspected to determine whether the write operation will effectively modify the destination of the write operation (i.e., whether a net change will occur). Those ineffective write operations are not performed. Preventing performance of the write operation includes not changing contents of locations in a memory hierarchy that correspond to the destination of the write operation.

Abstract: In a shared memory system, ineffective write operations (“dead stores”) can be handled in a manner to reduce unnecessary consumption of resources. In a shared memory system, when a non-owning processing unit requests data from a shared memory location owned by another processing unit, the memory controller for the shared memory requests a most current copy of the data from the owner processing unit. Instead of the owner processing unit reflexively sending its data to the memory controller, the owner processing unit determines whether the data has been changed, and, if it has not changed, transmits indication of such to the memory controller. Since the data has not changed, then the data at the shared memory location is proper and can be sent to satisfy the requesting processing unit.

Abstract: Predicting address matches between a read type operation and a write type operation based on address representations allows for efficient RAW bypass. The spatial locality characteristic of code allows for address match prediction with address representations that are smaller than the actual addresses, thus allowing for faster comparison. Operations for performing the RAW bypass commence upon predicting an address match. While these operations are being performed, other operations for verifying the prediction are performed. If the address match prediction is verified, then the RAW bypass has been performed without hindrance. If the address match is proved incorrect, then the corresponding read type operation is reissued and/or re-executed.

Abstract: Encoding positional information to track dependencies among memory requests resident in a memory request buffer increases efficiency of submitting those requests to memory. With the encoded positional information representing dependencies, a mechanism that selects memory requests for submission to memory can select memory requests without being hindered by determining dependencies repeatedly. In addition, the encoded positional information can be update incident with return of service indication from memory for a memory request.

Abstract: A memory structure of a computer system receives an address tag associated with a computational value, generates a modified address which corresponds to the address tag using a compression function, and stores the modified address as being associated with the computational value. The address tag can be a physical address tag or a virtual address tag. The computational value (i.e., operand data or program instructions) may be stored in the memory structure as well, such as in a cache associated with a processing unit of the computer system. For such an implementation, the compressed address of a particular cache operation is compared to existing cache entries to determine which a cache miss or hit has occurred. In another exemplary embodiment, the memory structure is a memory disambiguation buffer associated with at least one processing unit of the computer system, and the compressed address is used to resolve load/store collisions.