Patents by Inventor Balakumar Rajendran

Balakumar Rajendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11188511
    Abstract: Systems and methods are disclosed for a self-indexing removable storage device. In certain embodiments, the removable storage device is configured to be connected to a memory reader of a host device. The removable storage device comprises storage media, a controller configured to run firmware, and a buffer. The controller is configured to, while connected to a first host device, receive a write operation from the first host device, monitor changes to the storage media caused by the write operation, and update a file index stored on the removable storage device with the monitored changes. The controller is further configured to, in response to connecting the removable storage device to a memory reader of a second host device, provide the file index to an application on the second host device, and cause the application to display files on the storage media based on the file index.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narendhiran Cr, Muralitharan Jayaraman, Sivaraj Velusamy, Chandra Lakkimsetty, Vithya Kannappan, Balakumar Rajendran
  • Publication number: 20210326054
    Abstract: A storage system with privacy-centric multi-partitions and method for use therewith are provided. In one embodiment, a storage system comprises a memory configured to be partitioned into a plurality of partitions, wherein each partition is associated with its own boot block, and wherein each boot block is configured to boot any of the plurality of partitions. The storage system also comprises a controller configured to communicate with the memory and to: in response to a failure to boot one of the plurality of partitions with that partition's boot block, use a boot block of another one of the plurality of partitions to boot the one of the plurality of partitions; and restrict access to each of the plurality of partitions only to authenticated entities. Other embodiments are provided.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 21, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Muralitharan Jayaraman, Mayur Jain, Balakumar Rajendran, Narendhiran CR, Garvita Chauhan, Prashantha Krishna
  • Patent number: 11106518
    Abstract: A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 31, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Indu Kumari, Narendhiran CR, Abhinand Amarnath, Balakumar Rajendran, Muralitharan Jayaraman
  • Publication number: 20200387493
    Abstract: Systems and methods are disclosed for a self-indexing removable storage device. In certain embodiments, the removable storage device is configured to be connected to a memory reader of a host device. The removable storage device comprises storage media, a controller configured to run firmware, and a buffer. The controller is configured to, while connected to a first host device, receive a write operation from the first host device, monitor changes to the storage media caused by the write operation, and update a file index stored on the removable storage device with the monitored changes. The controller is further configured to, in response to connecting the removable storage device to a memory reader of a second host device, provide the file index to an application on the second host device, and cause the application to display files on the storage media based on the file index.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 10, 2020
    Inventors: Narendhiran CR, Muralitharan Jayaraman, Sivaraj Velusamy, Chandra Lakkimsetty, Vithya Kannappan, Balakumar Rajendran
  • Publication number: 20200278896
    Abstract: A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Indu Kumari, Narendhiran CR, Abhinand Amarnath, Balakumar Rajendran, Muralitharan Jayaraman
  • Patent number: 10713157
    Abstract: A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 14, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eyal Widder, Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, Indu Kumari, Abhinand Amarnath, Rohit Sathyanarayan
  • Publication number: 20190370167
    Abstract: A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Eyal Widder, Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, lndu Kumari, Abhinand Amarnath, Rohit Sathyanarayan
  • Patent number: 10275170
    Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, Satya Kesav Gundabathula, Ramkumar Ramamurthy, Rohit Sathyanarayan
  • Publication number: 20180293014
    Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, Satya Kesav Gundabathula, Ramkumar Ramamurthy, Rohit Sathyanarayan