Patents by Inventor Balasubramanian S. Pranatharthi Haran
Balasubramanian S. Pranatharthi Haran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230154784Abstract: A semiconductor device is provided. The semiconductor device includes a protective liner, and a buried power rail on a first portion of the protective liner, wherein the protective liner is on opposite sides of the buried power rail. The semiconductor device further includes a source/drain on a second portion of the protective liner, wherein the source/drain is offset from the buried power rail, and a source/drain contact on the source/drain and in electrical communication with the buried power rail.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Inventors: Ruilong Xie, Julien Frougier, Takeshi Nogami, Roy R. Yu, Balasubramanian S. Pranatharthi Haran
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Patent number: 11430651Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.Type: GrantFiled: April 20, 2018Date of Patent: August 30, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
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Patent number: 11355633Abstract: A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.Type: GrantFiled: January 3, 2020Date of Patent: June 7, 2022Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Ruilong Xie, Chun-Chen Yeh, Balasubramanian S Pranatharthi Haran
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Patent number: 11302637Abstract: An integrated circuit (IC) structure includes a dielectric layer extending along a first axis to define a length and a second axis orthogonal to the first axis to define a width. A dual-metal via is embedded in the dielectric layer. The dual-metal via includes via sidewalls surrounding a via core. An electrically conductive line extends along the first axis and on an upper surface of the dual-metal via. A side portion of the via core is co-planar with a sidewall of the electrically conductive line.Type: GrantFiled: August 14, 2020Date of Patent: April 12, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Balasubramanian S. Pranatharthi Haran, Devika Sil, Takeshi Nogami
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Publication number: 20220051976Abstract: An integrated circuit (IC) structure includes a dielectric layer extending along a first axis to define a length and a second axis orthogonal to the first axis to define a width. A dual-metal via is embedded in the dielectric layer. The dual-metal via includes via sidewalls surrounding a via core. An electrically conductive line extends along the first axis and on an upper surface of the dual-metal via. A side portion of the via core is co-planar with a sidewall of the electrically conductive line.Type: ApplicationFiled: August 14, 2020Publication date: February 17, 2022Inventors: Balasubramanian S. Pranatharthi Haran, Devika Sil, Takeshi Nogami
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Patent number: 11189528Abstract: A method is presented for constructing interconnects by employing a subtractive etch process. The method includes forming a plurality of first conductive lines within an interlayer dielectric, depositing dielectric layers over the plurality of first conductive lines, depositing a photoresist layer over the dielectric layers, patterning the photoresist layer to create vias to top surfaces of one or more of the plurality of first conductive lines, and depositing a conductive material such that the conductive material fills the vias and provides for a sheet of metal for second conductive lines formed above the first conductive lines.Type: GrantFiled: April 22, 2020Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Christopher Arnold, Balasubramanian S. Pranatharthi Haran, Takeshi Nogami
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Patent number: 11171054Abstract: A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.Type: GrantFiled: April 1, 2020Date of Patent: November 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Son Nguyen, Rudy J. Wojtecki, Noel Arellano, Alexander Edward Hess, Thomas Jasper Haigh, Jr., Cornelius Brown Peethala, Balasubramanian S. Pranatharthi Haran
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Patent number: 11164782Abstract: A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins upon a substrate, forming a plurality of epitaxially grown source-drain regions upon the fins, forming a plurality of device gates upon the fins, the device gates disposed between the epitaxially grown source-drain regions, forming a trench exposing at least one epitaxially grown source-drain region, masking at least a portion of the exposed epitaxially grown source-drain region, forming a gate trench exposing at least a portion of a device gate and gate spacer, forming a metallization layer between the epitaxially grown source-drain region and the device gate, selectively recessing the metallization layer, forming a conductive layer upon the metallization layer, and forming a dielectric cap above the conductive layer.Type: GrantFiled: January 7, 2020Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Ruilong Xie, Balasubramanian S Pranatharthi Haran, Dechao Guo, Nicolas Loubet, Alexander Reznicek
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Publication number: 20210335665Abstract: A method is presented for constructing interconnects by employing a subtractive etch process. The method includes forming a plurality of first conductive lines within an interlayer dielectric, depositing dielectric layers over the plurality of first conductive lines, depositing a photoresist layer over the dielectric layers, patterning the photoresist layer to create vias to top surfaces of one or more of the plurality of first conductive lines, and depositing a conductive material such that the conductive material fills the vias and provides for a sheet of metal for second conductive lines formed above the first conductive lines.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: John Christopher Arnold, Balasubramanian S. Pranatharthi Haran, Takeshi Nogami
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Patent number: 11152464Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having self-aligned isolations. In a non-limiting embodiment of the invention, a first gate stack is formed over channel regions of a first nanosheet stack. A second gate stack is formed over channel regions of a second nanosheet stack adjacent to the first nanosheet stack. An isolation pillar is positioned between the first gate stack and the second gate stack. The isolation pillar includes a top portion having a first width and a bottom portion having a second width less than the first width.Type: GrantFiled: March 27, 2020Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Balasubramanian S. Pranatharthi Haran, Ruilong Xie, Veeraraghavan S. Basker, Robert Robison
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Publication number: 20210313228Abstract: A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Inventors: Son Nguyen, Rudy J. Wojtecki, Noel Arellano, Alexander Edward Hess, Thomas Jasper Haigh, JR., Cornelius Brown Peethala, Balasubramanian S. Pranatharthi Haran
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Publication number: 20210305361Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having self-aligned isolations. In a non-limiting embodiment of the invention, a first gate stack is formed over channel regions of a first nanosheet stack. A second gate stack is formed over channel regions of a second nanosheet stack adjacent to the first nanosheet stack. An isolation pillar is positioned between the first gate stack and the second gate stack. The isolation pillar includes a top portion having a first width and a bottom portion having a second width less than the first width.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Balasubramanian S. Pranatharthi Haran, Ruilong Xie, Veeraraghavan S. Basker, Robert ROBISON
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Publication number: 20210305093Abstract: A semiconductor structure is provided including a gate cut region in which the contact trench size has been optimized to increase local interconnect connectivity. The semiconductor structure can include at least one gate structure located laterally adjacent to a gate cut region. At least one metal-containing contact structure is located in the gate cut region, wherein the at least one at least one metal-containing contact structure is confined by a pair of gate dielectric spacers, wherein a first gate dielectric spacer of the pair of gate dielectric spacers has a first width and is located laterally adjacent to the at least one gate structure, and a second gate dielectric spacer of the pair of gate dielectric spacers has a second width and is located laterally adjacent to the at least one metal-containing contact structure, wherein the first width is greater than the second width.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Alexander Reznicek, Balasubramanian S. Pranatharthi Haran, Praneet Adusumilli, Ruilong Xie
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Patent number: 11133217Abstract: A semiconductor structure is provided including a gate cut region in which the contact trench size has been optimized to increase local interconnect connectivity. The semiconductor structure can include at least one gate structure located laterally adjacent to a gate cut region. At least one metal-containing contact structure is located in the gate cut region, wherein the at least one at least one metal-containing contact structure is confined by a pair of gate dielectric spacers, wherein a first gate dielectric spacer of the pair of gate dielectric spacers has a first width and is located laterally adjacent to the at least one gate structure, and a second gate dielectric spacer of the pair of gate dielectric spacers has a second width and is located laterally adjacent to the at least one metal-containing contact structure, wherein the first width is greater than the second width.Type: GrantFiled: March 27, 2020Date of Patent: September 28, 2021Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Balasubramanian S. Pranatharthi Haran, Praneet Adusumilli, Ruilong Xie
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Publication number: 20210210384Abstract: A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins upon a substrate, forming a plurality of epitaxially grown source-drain regions upon the fins, forming a plurality of device gates upon the fins, the device gates disposed between the epitaxially grown source-drain regions, forming a trench exposing at least one epitaxially grown source-drain region, masking at least a portion of the exposed epitaxially grown source-drain region, forming a gate trench exposing at least a portion of a device gate and gate spacer, forming a metallization layer between the epitaxially grown source-drain region and the device gate, selectively recessing the metallization layer, forming a conductive layer upon the metallization layer, and forming a dielectric cap above the conductive layer.Type: ApplicationFiled: January 7, 2020Publication date: July 8, 2021Inventors: Ruilong Xie, Balasubramanian S Pranatharthi Haran, Dechao Guo, Nicolas Loubet, Alexander Reznicek
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Publication number: 20210210632Abstract: A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.Type: ApplicationFiled: January 3, 2020Publication date: July 8, 2021Inventors: Alexander Reznicek, Ruilong Xie, Chun-Chen Yeh, Balasubramanian S. Pranatharthi Haran
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Patent number: 10600638Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.Type: GrantFiled: October 24, 2016Date of Patent: March 24, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
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Patent number: 10586741Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.Type: GrantFiled: May 30, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
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Publication number: 20180240871Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.Type: ApplicationFiled: April 20, 2018Publication date: August 23, 2018Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
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Publication number: 20180122710Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.Type: ApplicationFiled: May 30, 2017Publication date: May 3, 2018Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang