Abstract: A method for data regeneration of protected data is provided wherein an error rate of a reception signal with error correcting code is identified. A sampling time and a decision threshold are provisionally varied in a predetermined range until an optimum sampling time and an optimum decision threshold are recovered by identifying the transmission error during this procedure. As a result, additional transmission errors have no influence due to the error correction.

Abstract: A phase-locked loop for controlling the phase of an output signal S2 dependent on a reference signal S1 with only a small phase timing error has a sampling circuit for sampling the reference signal S1 with the output signal S2 and for generating a sampling signal S1A, a jitter modulation circuit (3) for generating a sampling signal S1AJ delayed by a defined time duration and for alternating output of the undelayed sampling signal S1A and the delayed sampling signal S1AJ, a phase detector for acquiring an average phase difference between the output signal S2 and the delayed and undelayed sampling signals S1A and S1AJ, and a controllable oscillator for generating the output signal S2 with a frequency that is controllable dependent on the average phase difference acquired by the phase detector.

Abstract: A digital signal multiplex device converts k pleisochronic 564.992 Mbit/s signals or 4.multidot.k plesiochronic 139.264 Mbit/s signals or signals of both types into synchronous intermediate time division multiplex signals of a bit rate of 600.832 Mbit/s or, respectively, 621.776 Mbit/s, the conversion occurring by way of a special pulse frame having 544 or, respectively, 1056 time slots. The device then interlaces these intermediate time division multiplex signals pulse-frame wise with a multiplexer. A conversion in the opposite direction occurs in demultiplexing. The digital signal multiplex device may be employed as a line multiplexer in line terminal equipment for light wave guide links.

Abstract: A digital signal distributor for time division multiplex signals having the same frame format and for discrete channel signals has frame adaptors for synchronizing and storing the time division multiplex signals, and memories for the discrete channel signals, the frame adaptors and memories being provided following the inputs for the time division multiplex channels. The circuit further includes a distributor unit having an operator interface connected to the frame adaptors and the memories by first bus lines and first discrete lines. A clock pulse generator controls cyclical feeding of the stored code words into the first bus and first discrete lines. Second bus and second discrete lines are connected to an output of the distributor unit and transmit the time division multiplex output signals and the discrete signals to outputs of the circuit.