Patents by Inventor Balkaran Gill

Balkaran Gill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250216441
    Abstract: An aging detection circuit includes a sensor circuit and a reference circuit. The sensor circuit runs constantly with the operation of the device to be monitored. The sensor circuit can generate a sensor count. The reference circuit is turned off unless enabled for measurement of the device to be monitored. The reference circuit can generate a reference count. The aging detection circuit can include circuitry to determine the aging of the device to be monitored based on a difference between the sensor counter and the reference counter.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Minki CHO, Balkaran GILL
  • Publication number: 20240333289
    Abstract: The disclosure is directed to methods, a standard cell, and a system for forming a logic gate with reduced aging including organizing a plurality of transistors to provide a logic function for the logic gate, identifying a least one transistor in the plurality of transistors having a voltage swing to an output above a predetermined threshold, and coupling a voltage dividing transistor to the at least one transistor to reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Minki Cho, Balkaran Gill
  • Publication number: 20240235545
    Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
    Type: Application
    Filed: October 23, 2022
    Publication date: July 11, 2024
    Inventors: Minki Cho, Balkaran Gill, Anisur Rahman, Ketul B. Sutaria
  • Publication number: 20240137016
    Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
    Type: Application
    Filed: October 22, 2022
    Publication date: April 25, 2024
    Inventors: Minki Cho, Balkaran Gill, Anisur Rahman, Ketul B. Sutaria
  • Patent number: 11662376
    Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Ketul B. Sutaria, Balkaran Gill
  • Publication number: 20220368122
    Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) TO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Raj Singh Dua, Sanjay Joshi, Harry Muljono, Balkaran Gill
  • Patent number: 11444445
    Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Raj Singh Dua, Sanjay Joshi, Harry Muljono, Balkaran Gill
  • Publication number: 20220221507
    Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 14, 2022
    Inventors: Ketul B. Sutaria, Balkaran Gill
  • Patent number: 11287467
    Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Ketul B. Sutaria, Balkaran Gill
  • Publication number: 20210391703
    Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.
    Type: Application
    Filed: December 17, 2020
    Publication date: December 16, 2021
    Applicant: Intel Corporation
    Inventors: Raj Singh Dua, Sanjay Joshi, Harry Muljono, Balkaran Gill
  • Publication number: 20200408834
    Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.
    Type: Application
    Filed: April 9, 2020
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Ketul B. Sutaria, Balkaran Gill
  • Patent number: 10848134
    Abstract: An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Balkaran Gill, Norbert R. Seifert, Shah M. Jahinuzzaman, Randy L. Allmon
  • Patent number: 10803400
    Abstract: A self-adaptive security framework for a device is disclosed. A first security level for a device is set wherein the first security level comprises procedures that authenticate a user and allow the user to access the device. Input from sensors associated with the device may be received at a contextual sensing engine, wherein the input at least includes location data, and wherein at least a portion of the input is related to a physical setting where the device is located. A threat level for the device is determined in the physical setting via the contextual sensing engine based on analyzing the input. The first security level is altered to a second security level to provide an altered threat response for the device based on the threat level wherein the second security level has different procedures to authenticate the user compared to the first security level.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Suraj Sindia, Lital Shiryan, Tamir Damian Munafo, Santosh Ghosh, Balkaran Gill
  • Patent number: 10592331
    Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Clark N. Vandam, Balkaran Gill, Junho Song, Suriya Ashok Kumar, Kasyap Pasumarthi
  • Patent number: 10229570
    Abstract: Technologies for detecting a physical assault against a user include one or more clothing sensor modules coupled to a garment of the user. Each clothing sensor module is configured to produce sensor data indicative of the removal of the garment from the user and determine whether a physical assault is presently occurring against the user using an assault detection model with the sensor data as an input to the assault detection model. In response to a determination of the physical assault against the user, the clothing sensor module is configured to alert a trust party.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Balkaran Gill, Suraj Sindia, Zhen Yao, Mariano Phielipp
  • Publication number: 20180365098
    Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Clark N. VANDAM, Balkaran GILL, Junho SONG, Suriya ASHOK KUMAR, Kasyap PASUMARTHI
  • Patent number: 10114981
    Abstract: Apparatus, method, and system for remotely affecting the functionality and lifetime of an integrated circuit are described herein. One embodiment of a method includes: tracking a plurality of operational metrics relating to a monitored device, sending one or more of the plurality of operational metrics to a remote monitor and responsively receiving a command generated by the remote monitor, generating a threat level based on the plurality of operational metrics and the command, and performing a derating action based on the threat level. The command from the remote monitor may be generated by the remote monitor based, at least in part, on the one or more of the plurality of operational metrics. Alternatively, the command may be generated based on information obtained independently by the remote monitor and not based on the one or more of the plurality of operational metrics.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Robert F. Kwasnick, Suraj Sindia, Clark N. Vandam, Balkaran Gill
  • Patent number: 10078544
    Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.
    Type: Grant
    Filed: December 19, 2015
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Clark N. Vandam, Balkaran Gill, Junho Song, Suriya Suriya Ashok Kumar, Kasyap Pasumarthi
  • Publication number: 20180189522
    Abstract: Apparatus, method, and system for remotely affecting the functionality and lifetime of an integrated circuit are described herein. One embodiment of a method includes: tracking a plurality of operational metrics relating to a monitored device, sending one or more of the plurality of operational metrics to a remote monitor and responsively receiving a command generated by the remote monitor, generating a threat level based on the plurality of operational metrics and the command, and performing a derating action based on the threat level. The command from the remote monitor may be generated by the remote monitor based, at least in part, on the one or more of the plurality of operational metrics. Alternatively, the command may be generated based on information obtained independently by the remote monitor and not based on the one or more of the plurality of operational metrics.
    Type: Application
    Filed: December 31, 2016
    Publication date: July 5, 2018
    Inventors: Robert F. Kwasnick, Suraj Sindia, Clark N. Vandam, Balkaran Gill
  • Publication number: 20180190094
    Abstract: Technologies for detecting a physical assault against a user include one or more clothing sensor modules coupled to a garment of the user. Each clothing sensor module is configured to produce sensor data indicative of the removal of the garment from the user and determine whether a physical assault is presently occurring against the user using an assault detection model with the sensor data as an input to the assault detection model. In response to a determination of the physical assault against the user, the clothing sensor module is configured to alert a trust party.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Balkaran Gill, Suraj Sindia, Zhen Yao, Mariano Philiepp