Abstract: In preferred embodiments, a supplier enablement method including the steps of identifying and assessing capabilities of potential suppliers; engaging (pre-qualifying) selected potential suppliers; and enabling automated transactions (e.g., purchase orders and billing) between a buyer and each engaged supplier. Preferred embodiments of the method implement supplier enablement in three phases: supplier selection by a buyer; activation of each selected supplier; and management of relationships between the buyer and each selected supplier. Preferably, each phase has three subphases: the supplier selection phase includes identification of potential suppliers; assessment of their capabilities; and engagement of selected potential suppliers; the activation phase includes registration of each engaged supplier; content provision; and enablement of transaction business documents (e.g.

Abstract: A method and apparatus is disclosed for detecting edge-sensitive behavior from HDL descriptions of a circuit and inferring a hardware implementation of that behavior as a generalized edge-triggered D-type flip-flop with asynchronous set and clear inputs. The invention detects the edge-sensitive behavior from directed acyclic graphs (DAGS) that represent the individual signal nets of the circuit as affected by each process defined in the HDL description of the circuit. The invention then modifies each DAG to infer the asychronous control expressions and the data input expression necessary to control generalized flip-flop to emulate the behavior of the net represented by the DAG. The invention then creates a symbolic hardware implementation of the net's behavior using the D-type flip-flop and any combinational logic necessary to produced the inferred control signals.

Abstract: A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected parameter, such as circuit timing, circuit power consumption, or circuit area. Relying upon the set of cell instance performance values, a problematic component within the circuit is identified for replacement. A set of functionally equivalent candidate components are then identified. Each candidate component is analyzed with respect to the selected parameter. The analysis identifies an optimally performing candidate component. An instance of the optimally performing candidate component is then substituted into the netlist for the problematic component to improve the performance of the circuit.

Abstract: A method and apparatus for characterizing the timing behavior of datapath in integrated circuit design and fabrication. A set of circuit specifications for an integrated circuit are developed and described in a hardware description language (HDL) description. A datapath library including datapath cells and a gate library including primitive gate cells are provided, and a netlist is synthesized from the HDL description. The netlist is composed of datapath cells from the datapath library and primitive gate cells from the gate library. If a datapath cell instance in the netlist does not meet the timing constraints imposed by a user for the circuit, an alternative datapath cell instance can be substituted for that cell instance in a resynthesis and optimization step. An integrated circuit is preferably fabricated as specified by the resynthesized netlist. The netlist is preferably resynthesized multiple times in an iterative loop to optimize the netlist according to the constraints.

Abstract: A datapath circuit synthesizer converts an HDL circuit specification into a circuit netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic and control logic. The control logic is implemented in standard cells or gate arrays using a logic synthesizer. The datapath logic is optimally synthesized using a datapath synthesizer having a library of datapath elements, including both structural components and computational components, where some of the computational components are complex circuits having multiple, parallel outputs. Each computational component has associated therewith a set of one or more datapath expressions performed thereby. The received HDL circuit specification is converted into circuit data structures representing the circuit's datapath expressions and structural components. The datapath synthesizer locates all datapath elements in said library matching each such datapath expression and structural component.

Abstract: A method for fabricating an integrated circuit includes the steps of: (a) developing a set of circuit specifications for an integrated circuit; (b) encoding the set of circuit specifications in a hardware description language (HDL); (c) synthesizing a netlist including a sequential datapath with a datapath synthesizer from the HDL; and (d) fabricating an integrated circuit as specified by the netlist. A method for datapath synthesis includes the steps of: (a) providing a datapath library including sequential components and combinational components; (b) developing a set of circuit specifications for an integrated circuit; (c) encoding the set of circuit specifications in a HDL; (d) developing a number of IC expression trees derived from the HDL; (e) matching the IC expression trees with library expression trees derived from the datapath library to provide a map of matches; and (f) synthesizing according to the map to create a datapath netlist including both sequential datapaths and combinational datapaths.