Abstract: A method for detecting a presence of at least one face in at least one image is comprises creating an image patch map based on a plurality of face patches identified for at least one window in the in at least one image, estimating a bounding box, and searching within the bounding box to detect presence of the at least one face in the at least one image. The present disclosure discloses use of any classifier which works on top of any feature representation to identify face patches and then using a masking system to identify bounding boxes.

Abstract: A method for detecting a presence of at least one face in at least one image is comprises creating an image patch map based on a plurality of face patches identified for at least one window in the in at least one image, estimating a bounding box, and searching within the bounding box to detect presence of the at least one face in the at least one image. The present disclosure discloses use of any classifier which works on top of any feature representation to identify face patches and then using a masking system to identify bounding boxes.

Abstract: A method and apparatus for designing circuits uses parameterized Hardware Description Language (HDL) modules stored in a library. A datapath synthesizer accesses the library and assigns values to parameters to form specific implementations of the parameterized HDL modules. The specific implementations of the parameterized HDL modules are used by the datapath synthesizer to implement an HDL circuit description.

Abstract: A computer aided design system and method for automatically modifying a specified Hardware Description Language (HDL) characterization of a circuit to reduce signal delays on critical paths of the circuit is described. The specified circuit is analyzed with a logic synthesizer including a novel cell-based timing verifier that determines if a circuit meets specified timing requirements. Timing requirements are tested by computing a slack value for each node of the circuit at the component (macrocell) level, where the slack value represents the difference between the required arrival time of a signal at each circuit node and the computed worst case signal arrival time for the node. The output node having the most negative slack value is identified as a critical node. The HDL description of the circuit corresponding to the critical node is modified with a synthesis directive to substitute the original datapath cell with a better cell in order to improve the circuit's timing performance.