Patents by Inventor Balvinder Singh

Balvinder Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7314404
    Abstract: A burnishing head comprises at least two rails, each rail having an inner wall and an outer wall. The outer walls are at an angle relative to one another and relative to a central axis of the burnishing head. This angle permits the burnishing head to exhibit improved recovery time if it contacts a disk being burnished. The rail walls are vertical, and the corner between the rail walls and the top surface of the rails is sharp.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: January 1, 2008
    Assignees: Komag, Inc., Ahead Magnetics, Inc.
    Inventors: Balvinder Singh, Howard Temple, Rohini Patel, legal representative, Ravi Patel, legal representative, Geera Peters, legal representative, Jayadev Patel, deceased
  • Publication number: 20070190907
    Abstract: A burnishing head comprises at least two rails, each rail having an inner wall and an outer wall. The outer walls are at an angle relative to one another and relative to a central axis of the burnishing head. This angle permits the burnishing head to exhibit improved recovery time if it contacts a disk being burnished. The rail walls are vertical, and the corner between the rail walls and the top surface of the rails is sharp.
    Type: Application
    Filed: April 7, 2006
    Publication date: August 16, 2007
    Inventors: Balvinder Singh, Howard Temple, Jayadev Patel
  • Publication number: 20050047325
    Abstract: A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 3, 2005
    Applicant: Sasken Communication Technologies Ltd.
    Inventors: Balvinder Singh, Suyog Moogi
  • Patent number: 6604166
    Abstract: A memory architecture is provided to enable parallel access along any dimension of an n-dimensional data array. To enable parallel access of s data elements along any dimension, the data elements of n-dimensional data array are mapped to s parallel memory banks in such a way that consecutive s data elements along any dimension are mapped to different memory banks. This mapping is defined by two functions, which define the memory bank number and location within a memory bank for each data element in n-dimensional data array. The necessary and sufficient conditions, which the mapping functions should satisfy in order to enable parallel data access, are described. These generic function pairs are described for all combinations of (n, s). Two particular instances of the mapping, namely circular permutation (rotation) along 0th dimension and dyadic permutation along 0th dimension have been discussed in detail.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: August 5, 2003
    Assignee: Silicon Automation Systems Limited
    Inventors: Soumya Jana, Pankaj Bansal, Balvinder Singh