Patents by Inventor Balwinder Singh Soni
Balwinder Singh Soni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11835991Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.Type: GrantFiled: March 22, 2021Date of Patent: December 5, 2023Assignee: STMicroelectronics International N.V.Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan
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Publication number: 20230105305Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.Type: ApplicationFiled: December 9, 2022Publication date: April 6, 2023Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan SRINIVASAN, Balwinder Singh SONI, Avneep Kumar GOYAL
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Publication number: 20230042541Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.Type: ApplicationFiled: July 27, 2021Publication date: February 9, 2023Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan SRINIVASAN, Balwinder Singh SONI, Avneep Kumar GOYAL
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Patent number: 11557364Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.Type: GrantFiled: July 27, 2021Date of Patent: January 17, 2023Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Balwinder Singh Soni, Avneep Kumar Goyal
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Publication number: 20220300389Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan
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Patent number: 10944407Abstract: A transmitter circuit for use in a source synchronous type interface includes a flip-flop having a data input configured to receive serial data, a clock input configured to receive a source clock and a data output coupled to a data line. A first multiplexer has a first input configured to receive the source clock, a second input configured to receive a phase shifted clock (shifted by ninety degrees from the source clock), and a clock output coupled to a clock line. A control circuit operates to control selection by the first multiplexer of the source clock as a transmit clock sent over the clock line for a delay on clock at destination implementation. Alternatively, the control circuit causes selection by the first multiplexer of the phase shifted clock as the transmit clock sent over the clock line if the system is configured for a delay on clock at source implementation.Type: GrantFiled: June 3, 2020Date of Patent: March 9, 2021Assignee: STMicroelectronics International N.V.Inventors: Balwinder Singh Soni, Dinesh Chandra Joshi
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Patent number: 10393804Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.Type: GrantFiled: October 25, 2018Date of Patent: August 27, 2019Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
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Patent number: 10228420Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.Type: GrantFiled: September 19, 2016Date of Patent: March 12, 2019Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
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Publication number: 20190064268Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
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Publication number: 20180080987Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.Type: ApplicationFiled: September 19, 2016Publication date: March 22, 2018Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
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Patent number: 8644447Abstract: A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.Type: GrantFiled: November 25, 2009Date of Patent: February 4, 2014Assignee: STMicroelectronics International N.V.Inventors: Chandra Bhushan Prakash, Balwinder Singh Soni
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Publication number: 20100128837Abstract: A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.Type: ApplicationFiled: November 25, 2009Publication date: May 27, 2010Applicant: STMicroelectronics Pvt. Ltd.Inventors: Chandra Bhushan Prakah, Balwinder Singh Soni