Abstract: The present invention provides a method of forming a first load having a first resistance level and a second load having a second resistance level in a common layer of polysilicon. In accordance with the method, a layer of polysilicon having a first resistance level is formed on a semiconductor circuit structure. A mask is then formed on the polysilicon layer to define areas of the polysilicon to be implanted with a dopant. The dopant is then implanted into the defined areas of the polysilicon to modify these areas to have a second resistance level. Selected areas of the polysilicon layer are then etched away to form first load regions having the first resistance level and second load regions having the second resistance level.

Abstract: A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

Abstract: A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned manner by use of a lateral etching technique to undercut the mask used for definition of the buried layers. In the process, the collector and base contacts of the bipolar devices and the corresponding conductivity-type sources and drains of the field effect transistors are combined to minimize processing steps. The process also includes a silicided polycrystalline silicon layer used to form resistors and contact the various transistors.