Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract: This disclosure relates to monitoring signal overshoot of an amplifier generated signal and automatically adjusting a quiescent current of the amplifier as a function of the monitored signal overshoot.

Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract: A differential line compensation apparatus, semiconductor chip and system are disclosed.

Abstract: This disclosure relates to monitoring signal overshoot of an amplifier generated signal and automatically adjusting a quiescent current of the amplifier as a function of the monitored signal overshoot.

Abstract: A voltage detection and sequencing circuit is provided, preferably on a single semiconductor chip, for applying a plurality of voltages to an electrical system in a predetermined sequence. The circuit includes a plurality of subsystems each adapted to detect one of a plurality of supply voltages at an input terminal and to supply the supply voltage to at least one output terminal in a predetermined sequence as controlled by a sequencing means.

Abstract: An apparatus includes a bidirectional data line to couple to a device and an impedance to provide an impedance matching between the data line and the device. In some embodiments, when a direction of data flow in the data line is away from the device, the impedance is of a first impedance value, and when the direction of the data flow is toward the device, the impedance is of a second impedance value. In one embodiment, the second impedance value is substantially zero.

Abstract: A differential line compensation apparatus, semiconductor chip and system are disclosed.

Abstract: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.

Abstract: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.

Abstract: There is provided apparatus for connecting between a data source or a data receiver and a data line. The apparatus comprises an impedance and an impedance controller arranged to continually adjust the value of the active impedance so as to control the relative impedances of the total source, the total source comprising the data source and the impedance, and the data line or of the total receiver, the total receiver comprising the data receiver and the impedance, and the data line. There is also provided a semiconductor chip, connectable to a data line, the semiconductor chip comprising the apparatus together with a data source or data receiver, as appropriate. There is also provided a method for controlling impedance matching between a data source or data receiver and a data line.

Abstract: A system for hardware intelligent speed monitoring and auto-retract is disclosed. The system contains a monitoring device that monitors the TACH (Tachometer) output of motor driver. The device provides a trigger to the signal processor and a retract mechanism to retract the actuator when the spindle motor speed is unexpectedly much higher or lower than normal speed. The system DSP (Digital Signal Processor) is unaware of such occurrence.

Abstract: A method for compensating digital samples of an asymmetric read signal is presented. The method involves reading a digital sample of an asymmetric read signal V(t) (160), generating a compensated sample at least when the digital sample requires compensation (164), and outputting either the digital sample (168) or the compensated sample (166). Also presented is an asymmetry correction block (158) of a read channel (144) of a disc drive (110) that includes an input (200), a level detector (202), a compensator (204), and an output (208). The level detector (202) and the compensator (204) receive the digital sample through the input (200). The level detector (202) determines whether the digital sample requires compensation. The compensator (204) generates a compensated sample at least when the digital sample requires compensation. The output (208) selectively outputs either the digital sample or the compensated sample.