Abstract: A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.

Abstract: A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist layer over the first sacrificial layer and filling the plurality of openings formed through the first sacrificial layer; forming a plurality of openings in the first photoresist layer, each one of the plurality of openings in the first photoresist layer overlying one of the openings in the first sacrificial layer and wherein each opening in the first sacrificial layer has a smaller cross-sectional area then the cross-sectional area of the overlying opening in the first photoresist layer; and etching the first layer through the openings in the first photoresist layer and the first sacrificial layer, comprising exposing the first layer to an etching material.

Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: A method for reducing a critical dimension of a photoresist pattern while improving a line spacing between distal end portions of pattern lines wherein the method includes providing a substrate including an overlying resist; exposing the resist to an activating light source; baking the resist in a first baking process followed by developing the resist in a first development process to form a first resist pattern; then baking the first resist pattern in a second baking process followed by developing the first resist pattern in a second development process to form a second resist pattern having reduced dimensions; and, then dry trimming the second resist pattern to form a final resist pattern with reduced dimensions compared to the second resist pattern.

Abstract: In the manufacture of a semiconductor, a DBARC layer is deposited upon a wafer to prevent reflection. A photo resist layer is deposited upon the DBARC layer and the wafer is selectively exposed to irradiation. The irradiation generates photo acid (H+ ions) in the exposed areas of the photo resist and DBARC. In order to provide better resolution in the DBARC for micro-features, an electric field is generated vertically through the coated wafer before or during post exposure baking (PEB) to create a uniform vertical distribution of H+ ions though the DBARC. The coated wafer is then developed to remove either the unexposed portions, or exposed portion of the DBARC. The cavities formed by the developer have side walls that are substantially vertical as a result of the uniform vertical distribution of the H+ ions.

Abstract: A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.

Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist layer over the first sacrificial layer and filling the plurality of openings formed through the first sacrificial layer; forming a plurality of openings in the first photoresist layer, each one of the plurality of openings in the first photoresist layer overlying one of the openings in the first sacrificial layer and wherein each opening in the first sacrificial layer has a smaller cross-sectional area then the cross-sectional area of the overlying opening in the first photoresist layer; and etching the first layer through the openings in the first photoresist layer and the first sacrificial layer, comprising exposing the first layer to an etching material

Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: In accordance with the objectives of the invention a new water soluble negative photoresist is provided for packing-and-unpacking (PAU) processing steps.

Abstract: In the manufacture of a semiconductor, a DBARC layer is deposited upon a wafer to prevent reflection. A photo resist layer is deposited upon the DBARC layer and the wafer is selectively exposed to irradiation. The irradiation generates photo acid (H+ ions) in the exposed areas of the photo resist and DBARC. In order to provide better resolution in the DBARC for micro-features, an electric field is generated vertically through the coated wafer before or during post exposure baking (PEB) to create a uniform vertical distribution of H+ ions though the DBARC. The coated wafer is then developed to remove either the unexposed portions, or exposed portion of the DBARC. The cavities formed by the developer have side walls that are substantially vertical as a result of the uniform vertical distribution of the H+ ions.

Abstract: A method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to increase the hole density of the packed mask. An insulation layer is formed to protect the first layer of material. The second mask, referred to an the unpacking mask, comprises openings at the same locations as the locations of the padding holes of the first mask, the openings provided in the second mask have slightly larger dimensions than the padding holes of the first mask. A first exposure is made using the packed mask, a second exposure of the same surface area is made using the unpacking mask. The unpacking mask is used to selectively cover the padding contact holes, resulting in the final image.

Abstract: A method for reducing a critical dimension of a photoresist pattern while improving a line spacing between distal end portions of pattern lines wherein the method includes providing a substrate including an overlying resist; exposing the resist to an activating light source; baking the resist in a first baking process followed by developing the resist in a first development process to form a first resist pattern; then baking the first resist pattern in a second baking process followed by developing the first resist pattern in a second development process to form a second resist pattern having reduced dimensions; and, then dry trimming the second resist pattern to form a final resist pattern with reduced dimensions compared to the second resist pattern.

Abstract: A new method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to increase the hole density of the packed mask. The second mask, referred to an the unpacking mask, comprises openings at the same locations as the locations of the padding holes of the first mask, the openings provided in the second mask have slightly larger dimensions than the padding holes of the first mask. A first exposure is made using the packed mask, a second exposure of the same surface area is made using the unpacking mask. The unpacking mask is used to selectively cover the padding contact holes, resulting in the final image.

Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: A method and system is disclosed for selectively forming photoresist patterns for making openings in a substrate. A layer of photoresist is deposited on the substrate which contains one or more types of photoresist dissolving agent generators. A first set of areas of the photoresist is exposed to a first light source through a first mask to activate a photoresist dissolving agent generator of a first type to release a first photoresist dissolving agent in the first set of areas. Then, a second set of areas of the photoresist is also exposed to a second light source through a second mask to activate a photoresist dissolving agent generator of a second type to release a second photoresist dissolving agent in the second set of areas. The second set of areas is a sub set of the first set of areas such that the first and second photoresist dissolving agents in the second set of areas neutralize each other to protect the second set of areas from being used as the patterns for forming the openings.

Abstract: A method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to increase the hole density of the packed mask. An insulation layer is formed to protect the first layer of material. The second mask, referred to an the unpacking mask, comprises openings at the same locations as the locations of the padding holes of the first mask, the openings provided in the second mask have slightly larger dimensions than the padding holes of the first mask. A first exposure is made using the packed mask, a second exposure of the same surface area is made using the unpacking mask. The unpacking mask is used to selectively cover the padding contact holes, resulting in the final image.

Abstract: A method is provided for removing sidelobes that are formed when patterning a positive photoresist layer with an Att. PSM, Alt. PSM or a binary mask with scattering bars. A water soluble negative tone photoresist is coated over the positive photoresist pattern and is exposed through a mask having small islands that correspond in shape, size and location to the small holes in the mask used to pattern the positive tone photoresist. After development, exposed negative tone photoresist covers sidelobes formed by the positive tone process. The negative tone photoresist functions as a mask for a subsequent etch transfer of the positive tone pattern into the substrate. A method of aligning openings in a positive tone pattern over the same openings in a negative tone pattern is also useful in preventing sidelobes in the positive tone photoresist from being transferred into the substrate.

Abstract: A method and system is disclosed for selectively forming a pattern for making openings in a substrate. A first set of openings are formed in a first photoresist layer coated on the substrate using a first mask. A developing bottom antireflective coating (BARC) layer is then formed over the first photoresist with the openings filled therewith. A second photoresist layer is formed over the BARC layer. A second set of openings are formed in the second photoresist layer using a second mask exposing the BARC layer directly underneath. The exposed part of the BARC layer is then removed. Subsequently, one or more openings of the first set in the first photoresist layer, after the exposed part of the BARC layer filled therein is removed, are used for forming the openings in the substrate.

Abstract: In accordance with the objectives of the invention a new water soluble negative photoresist is provided for packing-and-unpacking (PAU) processing steps.