Patents by Inventor Bang-Chien Ho
Bang-Chien Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7524607Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.Type: GrantFiled: March 10, 2006Date of Patent: April 28, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bang-Chien Ho, Jian-Hong Chen
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Patent number: 7399709Abstract: An image reversal method is described that removes the etch resistance requirement from a resist. A high resolution resist pattern comprised of islands, lines, or trenches is formed with a large process window by exposing through one or more masks including phase edge masks and optionally with resolution enhancement techniques. A complementary material replacement (CMR) layer comprised of an organic polymer or material such as fluorosilicate glass which has a lower etch rate than the resist is coated over the resist pattern. CMR and resist layers are etched simultaneously to provide an image reversed pattern in the CMR layer which is etch transferred into a substrate. The method avoids edge roughness like bird's beak defects in the etched pattern and is useful for applications including forming contact holes in dielectric layers, forming polysilicon gates, and forming trenches in a damascene process. It is also valuable for direct write methods where an image reversal scheme is desired.Type: GrantFiled: September 27, 2002Date of Patent: July 15, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Burn-Jeng Lin, Hua-Tai Lin, Ru-Gun Liu, Tsai-Sheng Gau, Bang-Chien Ho
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Patent number: 7253112Abstract: A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.Type: GrantFiled: August 10, 2004Date of Patent: August 7, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bang-Chien Ho, Jian-Hong Chen, Tsang-Jiuh Wu, Li-Te Lin, Li-Chih Chao, Hua-Tai Lin, Shyue-Sheng Lu
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Publication number: 20060154177Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.Type: ApplicationFiled: March 10, 2006Publication date: July 13, 2006Inventors: Bang-Chien Ho, Jian-Hong Chen
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Patent number: 7033735Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.Type: GrantFiled: November 17, 2003Date of Patent: April 25, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bang-Chien Ho, Jian-Hong Chen
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Publication number: 20050106493Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.Type: ApplicationFiled: November 17, 2003Publication date: May 19, 2005Inventors: Bang-Chien Ho, Jian-Hong Chen
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Publication number: 20050014362Abstract: A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.Type: ApplicationFiled: August 10, 2004Publication date: January 20, 2005Inventors: Bang-Chien Ho, Jian-Hong Chen, Tsang-Jiuh Wu, Li-Te Lin, Li-Chih Chao, Hua-Tai Lin, Shyue-Sheng Lu