Patents by Inventor Bang Nguyen

Bang Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150007666
    Abstract: A method of monitoring usage of a component of an aircraft can include: monitoring a usage of the component by using a torque measurement system to calculate torque events in a time period; categorizing the usage of the component by assigning a usage value based upon whether the number of torque events in the period of time is above or below a threshold; and determining a life used of the component.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Inventors: Brian Tucker, Tom Wood, Robert Wardlaw, Bang Nguyen, Allen Altman
  • Publication number: 20140166099
    Abstract: Crystalline photovoltaic (PV) cells and methods of manufacturing cells are described. One example method of manufacturing a PV cell includes depositing a plurality of first fingers on a crystalline silicon wafer. The first fingers extend in a first direction parallel to each other and comprise a substantially non-silver conductive material.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 19, 2014
    Inventors: Hongbin Fang, Bo Li, Hsiu-Wu Guo, Bang Nguyen
  • Publication number: 20060288156
    Abstract: An apparatus comprises a storage medium, an arm for positioning a recording head adjacent to the storage medium, and a controller for receiving objects and for selecting blocks on the storage medium to be written by the recoding head based on information in the objects. A method for storing objects is also provided. In another aspect, the invention provides a method for writing data in data storage devices. The method comprises: receiving access commands for objects, selecting blocks on a storage medium to be written by a recording head based on information in the objects, and writing data from the objects to the selected blocks.
    Type: Application
    Filed: June 16, 2005
    Publication date: December 21, 2006
    Applicant: Seagate Technology LLC
    Inventors: Wilson Fish, Bang Nguyen, Jack Mobley
  • Patent number: 6757812
    Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: June 29, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Daniel W. Green, Atul Dhablania, Jeffrey A. Lohman, Bang Nguyen
  • Patent number: 6599574
    Abstract: The present invention relates to the deposition of dielectric layers, and more specifically to a method and apparatus for forming dielectric layers such as borophosphosilicate glass (BPSG) having improved film uniformity, higher deposition rate, superior gap fill/reflow capability, and smoother surface morphology. The method forms a dielectric layer with a process using helium carrier gas that produces substantially less downstream residue than conventional methods and apparatus, thereby reducing the need for chamber cleaning and increasing throughput of processed wafers. The present invention utilizes helium instead of nitrogen as carrier gas in a process for forming a dielectric layer such as BPSG to provide various unexpected benefits. According to one aspect, the present invention forms a dielectric film on a substrate, and prolongs a period between chamber cleanings in a system by using helium which produces substantially less downstream and upstream residue than a process using nitrogen.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: July 29, 2003
    Assignee: Applied Materials Inc.
    Inventors: Ellie Yieh, Paul Gee, Li-Qun Xia, Francimar Campana, Shankar Venkataranan, Dana Tribula, Bang Nguyen
  • Patent number: 6405232
    Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: June 11, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Daniel W. Green, Atul Dhablania, Jeffrey A. Lohman, Bang Nguyen
  • Patent number: 6121164
    Abstract: A method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about -5.times.10.sup.8 dynes/cm.sup.2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: September 19, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Ellie Yieh, Xin Zhang, Bang Nguyen, Stuardo Robles, Peter Lee
  • Patent number: 6099647
    Abstract: The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: August 8, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Ellie Yieh, Li-Qun Xia, Paul Gee, Bang Nguyen
  • Patent number: 5994209
    Abstract: The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: November 30, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Ellie Yieh, Li-Qun Xia, Paul Gee, Bang Nguyen
  • Patent number: 5356722
    Abstract: A process for depositing void-free silicon oxide layers over stepped topography comprising depositing a first silicon oxide seed layer which is doped with nitrogen from a plasma of tetraethoxysilane and a nitrogen-containing gas, and depositing thereover a silicon oxide layer from a mixture of tetraethoxysilane, ozone and oxygen at low temperatures to produce a silicon oxide layer having improved properties.
    Type: Grant
    Filed: June 10, 1992
    Date of Patent: October 18, 1994
    Assignee: Applied Materials, Inc.
    Inventors: Bang Nguyen, Ellie Yieh, Maria Galiano