Patents by Inventor Bangrong XU

Bangrong XU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shift register unit and driving method thereof, scan driving circuit, array substrate and display device
    Patent number: 11361702
    Abstract: A shift register unit and a driving method thereof, a scan driving circuit, an array substrate and a display device. The shift register unit includes: an input circuit configured for setting the first node to a valid level in a case where the input terminal is at a valid level; a first reset control circuit configured for setting the second node to a valid level and setting the input terminal to an invalid level in a case where the reset terminal is at a valid level; an output circuit configured for setting the output terminal to a valid level by using a clock signal in a case where the first node is at the valid level; a reset circuit configured for setting the first node and the output terminal to an invalid level in a case where the second node is at a valid level.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 14, 2022
    Assignees: HEFEI BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongtao Guo, Guowei Chai, Fu Tang, Bangrong Xu
  • SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, SCAN DRIVING CIRCUIT, ARRAY SUBSTRATE AND DISPLAY DEVICE
    Publication number: 20210350738
    Abstract: A shift register unit and a driving method thereof, a scan driving circuit, an array substrate and a display device. The shift register unit includes: an input circuit configured for setting the first node to a valid level in a case where the input terminal is at a valid level; a first reset control circuit configured for setting the second node to a valid level and setting the input terminal to an invalid level in a case where the reset terminal is at a valid level; an output circuit configured for setting the output terminal to a valid level by using a clock signal in a case where the first node is at the valid level; a reset circuit configured for setting the first node and the output terminal to an invalid level in a case where the second node is at a valid level.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 11, 2021
    Inventors: Hongtao GUO, Guowei CHAI, Fu TANG, Bangrong XU