Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.

Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.

Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.

Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.

Abstract: A system is provided which simplifies and speeds up the process of designing a computer system by evaluating the components of the memory hierarchy for any member of a broad family of processors in an application-specific manner. The system uses traces produced by a reference processor in the design space for a particular cache design and characterizes the differences in behavior between the reference processor and an arbitrarily chosen processor. The differences are characterized as a series of dilation parameters which relate to how much the traces would expand because of the substitution of a target processor. In addition, the system characterizes the reference trace using a set of trace parameters that are part of a cache behavior model. The dilation and trace parameters are used to determine the factors for estimating the performance statistics of target processors with specific memory hierarchies.

Abstract: A parallel compiler maps iterations of a nested loop to processor elements in a parallel array and schedules a start time for each iteration such that the processor elements are fully utilized without being overloaded. The compiler employs an efficient and direct method for generating a set of iteration schedules that satisfy the following constraints: no more than one iteration is in initiated per processor element in a specified initiation interval, and a new iteration begins on each processor element nearly every initiation interval. Since the iteration scheduling method efficiently generates a set of schedules, the compiler can select an iteration schedule that is optimized based on other criteria, such as memory bandwidth, local memory size of each processor element, estimated hardware cost of each processor element, etc.