Abstract: An integrated circuit is disclosed which includes a start test mode circuit for generating a test mode start-up signal to cause the integrated circuit to enter a test mode, and an automatic reset circuit responsive to the test mode start-up signal for preventing the integrated circuit from erroneously entering a test mode during normal operation.

Abstract: The present invention relates to a reset signal generator adapted to be used with a microprocessor for generating a reset signal to initialize the microprocessor, which includes an oscillator to generate a fixed clock signal, a counter electrically connected to the oscillator for generating a cyclic signal in response to the fixed clock signal and outputting the reset signal at an end of a period of the cyclic signal, and a clear signal generating device electrically connected to the counter and outputting a clear signal for the counter in response to an output signal from the microprocessor. The present invention ensures that when the microprocessor is abnormal or down it will be initialized by the reset signal.