Abstract: A semiconductor structure, a fabricating method thereof, and a chip packing structure are provided. The disclosed semiconductor structure includes a printed circuit board, a chip packing structure, and a ball grid array connected between the printed circuit board and the chip packing structure. The ball grid array includes first solder balls each having a first lateral size, and second solder balls each having a second lateral size greater than the first lateral size. The second solder balls are located at corners of the ball grid array, respectively.

Abstract: The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL.

Abstract: The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL.

Abstract: The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.

Abstract: The present application provides a chip package structure and a fabrication method thereof, a memory and a memory system. The chip package structure includes a substrate, a chip on a side of the substrate, an energy storage material layer on a side of the chip opposite the substrate, and a package layer that includes a first portion covering the chip and a second portion covering the energy storage material layer. According to the present application, by disposing the energy storage material layer on a side of the chip, the energy storage material layer absorbs the heat generated by the chip, thereby improving the heat dissipation capability of the chip package structure for the chip.

Abstract: Examples of the present disclosure provide a package structure, the package structure including: a package substrate; a semiconductor device on the package substrate; and a molding layer over the semiconductor device, the molding layer having a plurality of grooves disposed at its surface.

Abstract: The present disclosure provides a package structure and its forming method, a memory system and its forming method. The package structure includes: a plastic encapsulation layer and a rib like structure, wherein, the rib like structure is located on the plastic encapsulation layer, and a bottom surface of the rib like structure is located on a top surface of the plastic encapsulation layer.

Abstract: In one example, the disclosed semiconductor structure includes a package substrate, a first chip, a conductive pillar and a second chip, wherein the package substrate has a first surface; the first chip is located on the first surface of the package substrate and electrically connected to the package substrate; the conductive pillar is located on the first surface of the package substrate and electrically connected to the package substrate; the second chip is located on a side of the first chip and the conductive pillar away from the package substrate and electrically connected to the conductive pillar; and an orthographic projection of the conductive pillar on the package substrate is located within a range of an orthographic projection of the first chip or the second chip on the package substrate. The chip package structure is configured for connection with a circuit board in the electronic device. Other examples are disclosed.

Abstract: A production equipment of phenethylamine includes a first reaction device; a second reaction device, wherein the second reaction device is connected to the first reaction device; a circulation device, wherein the circulation device is respectively connected to the first reaction device and the second reaction device; an acetone storage device; a centrifugal extraction device; a phenethylamine processing device; and a phenethylamine storage device. The first reaction device and the second reaction device have the same structure. A production method of phenethylamine is further provided, which uses transaminase as a catalyst, so that acetophenone and isopropylamine can flow through the transaminase to complete the reaction, the reaction is completed in one step, the production cycle is shortened, and the production cost is reduced.

Abstract: A manufacturing method of an integrated circuit (IC) packaging structure includes the following steps. One or a plurality of dies is disposed on a packaging substrate. An encapsulation material is formed on the packaging substrate. The encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate. At least one trench is formed in the encapsulation material. A heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench. The step of forming the heat dissipation structure includes the following steps. A first slurry is formed in the at least one trench, and a first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.

Abstract: The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.

Abstract: A manufacturing method of an integrated circuit (IC) packaging structure includes the following steps. One or a plurality of dies is disposed on a packaging substrate. An encapsulation material is formed on the packaging substrate. The encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate. At least one trench is formed in the encapsulation material. A heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench. The step of forming the heat dissipation structure includes the following steps. A first slurry is formed in the at least one trench, and a first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.

Abstract: An integrated circuit (IC) packaging structure includes a packaging substrate, one or a plurality of dies, an encapsulation material, at least one trench, and a heat dissipation structure. The one or the plurality of the dies is disposed on the packaging substrate. The encapsulation material is disposed on the packaging substrate and is configured to encapsulate the one or the plurality of the dies on the packaging substrate. The at least one trench is disposed in the encapsulation material. At least a part of the heat dissipation structure is disposed in the at least one trench. The cooling capability of the IC packaging structure may be improved by the heat dissipation structure without increasing the size of the IC packaging structure significantly.

Abstract: The present invention discloses a functionally integrated induction lamp comprising a bottom case and a top case. A PCB having a light control circuit is arranged therebetween, which is provided with an induction sensor for detecting moving objects or ambient light signals to trigger the induction LED lamp for emitting light and an induction LED lamp connected to the circuit. A light guide plate enabling the light emitted by the induction LED lamp to come out and a sensor shield are arranged on the top case. An outer surface of the sensor shield is connected transitionally to an outer surface of the light guide plate smoothly to form a curved surface, which can greatly improve its appearance. Meanwhile, the sensor shield is a Fresnel lens with a smooth outer surface and an inner surface having concave and convex texture, greatly improving the induction to moving human bodies.

Abstract: A method for pre-accessing a conference telephone is disclosed in the present invention. The method includes that: a network side detects a received call whose target is a main control party after the main control party initiates an encryption conference telephone; the call is not accessed if the call is a non-encryption conversation; the call is allowed to be accessed if the call is an encryption conversation. A system for pre-accessing a conference telephone is also disclosed in the present invention, wherein, the system includes a pre-accessing processing unit and a call type detection unit of the network side. A network side device is also disclosed in the present invention. The present invention realizes the pre-accessing of the encryption conference telephone, thereby improving security of the encryption conversation as well as avoiding the problem that a user is frequently affected when performing the encryption conference telephone.

Abstract: The present invention relates to mobile terminals and provides a method, device, and terminal for installing a browser plug-in. The method includes: receiving an instruction of installing a browser plug-in which is applied in a designated browser; and judging whether the browser plug-in is legal according to digital signature information of the browser plug-in and browser information of the designated browser, if yes, installing the browser plug-in, otherwise, rejecting the installation of the browser plug-in. At the beginning of the installation of the browser plug-in, the browser plug-in is verified according to the digital signature information of the browser plug-in and the browser information of the designated browser corresponding to the browser plug-in, thus, the legality and traceability of the browser plug-in can be determined to prevent the harmful browser plug-in from calling API of the mobile terminal at random and further to improve the safety of the mobile terminal.