Patents by Inventor BAOKANG WANG

BAOKANG WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250094901
    Abstract: The present invention provides an electric power material distribution and allocation method based on an optimized branch and bound method, including: sorting the distribution of each batch of electric power materials to obtain a material set R; screening available vehicle data to obtain a vehicle deadweight set W and a vehicle unique identification set C; determining whether available vehicles meet requirements; and using an optimized queued branch and bound method to obtain an optimal distribution and allocation scheme. According to the present invention, scientific scheme support is provided for the distribution and allocation of the electric power materials, the scientificity of the distribution of power grid materials is improved, the influence of human factors is reduced, the utilization rate of distribution vehicles is increased, the distribution cost of the materials is reduced, and the economic benefit is improved.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 20, 2025
    Inventors: Xiao ZHAO, Baokang WANG, Jiayong YANG, Yun ZHANG, Yunjiang YU, Can SUN, Cong ZHU, Honghao DAI, Tianji XU, Zixiang YAN
  • Publication number: 20240428844
    Abstract: Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.
    Type: Application
    Filed: September 10, 2024
    Publication date: December 26, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: BAOKANG WANG, TAKUYA MIYAGI
  • Patent number: 12125519
    Abstract: Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: October 22, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Baokang Wang, Takuya Miyagi
  • Publication number: 20240233806
    Abstract: Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.
    Type: Application
    Filed: October 19, 2022
    Publication date: July 11, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: BAOKANG WANG, TAKUYA MIYAGI
  • Publication number: 20240135984
    Abstract: Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: BAOKANG WANG, TAKUYA MIYAGI
  • Patent number: 11830538
    Abstract: Apparatuses, systems, and methods for data timing alignment in stacked memory. The memory a number of core dice stacked on an interface die. The core and interface die each include adjustable delay circuits along each of a delay and native path. A state machine operates interface and core aligner control circuits to set values of the delay(s) in the interface and core dice respectively. The state machine may initialize the delays and then enter a maintenance state where averaging is used to determine when to adjust the delay in the core dice. If an overflow or underflow condition is met, the state machine may cycle between adjusting the delay in the interface die and adjusting the delays in the core dice without averaging until the overflow and underflow conditions are no longer met and the maintenance state is returned to.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: November 28, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Baokang Wang
  • Publication number: 20230206984
    Abstract: Apparatuses, systems, and methods for data timing alignment in stacked memory. The memory a number of core dice stacked on an interface die. The core and interface die each include adjustable delay circuits along each of a delay and native path. A state machine operates interface and core aligner control circuits to set values of the delay(s) in the interface and core dice respectively. The state machine may initialize the delays and then enter a maintenance state where averaging is used to determine when to adjust the delay in the core dice. If an overflow or underflow condition is met, the state machine may cycle between adjusting the delay in the interface die and adjusting the delays in the core dice without averaging until the overflow and underflow conditions are no longer met and the maintenance state is returned to.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: BAOKANG WANG