Patents by Inventor Baolei Wu
Baolei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12108682Abstract: Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.Type: GrantFiled: July 27, 2021Date of Patent: October 1, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Baolei Wu, Xiaoguang Wang, Yulei Wu
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Patent number: 12035539Abstract: The present application provides a magnetic memory and a reading/writing method thereof. The magnetic memory includes at least one cell layer, the cell layer including: a plurality of paralleled first conductors located in a first plane; a plurality of paralleled second conductors located in a second plane, the first plane being parallel to the second plane, a projection of the second conductor on the first plane intersecting with the first conductor; a plurality of memory elements arranged between the first plane and the second plane, the memory element including a magnetic tunnel junction and a bidirectional gating device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction being connected to the first conductor, the bidirectional gating device being connected to the second conductor, and the bidirectional gating device being configured to be turned on when a threshold voltage and/or a threshold current are/is applied.Type: GrantFiled: September 21, 2021Date of Patent: July 9, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Baolei Wu, Xiaoguang Wang, Yulei Wu
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Patent number: 11930644Abstract: The present disclosure provides a semiconductor structure and a storage circuit that implements the storage structure of a magnetoresistive random access memory (MRAM) based on a dynamic random access memory (DRAM) fabrication platform.Type: GrantFiled: August 3, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Er-Xuan Ping, Xiaoguang Wang, Baolei Wu, Yulei Wu
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Patent number: 11929105Abstract: The present application makes public a magnetic memory and a reading/writing method thereof, which magnetic memory comprises at least one cell layer, and the cell layer includes a plurality of parallel second wires that are disposed in a second plane, the first plane being parallel to the second plane, and projections of the second wires onto the first plane intercrossing the first wires; a plurality of storage elements that are disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bi-directional gating components connected in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first wires, the bi-directional gating components being connected to the second wires, and the bi-directional gating components being configured to be conductive upon application of a threshold voltage and/or a threshold current.Type: GrantFiled: October 18, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Baolei Wu, Xiaoguang Wang, Yulei Wu
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Patent number: 11875835Abstract: A memory and a read and write method of memory can prevent the magnetic random-access memory (MRAM) from being easily damaged or degraded by excessive write current during use, and increase memory integration density. The memory includes: a storage unit, comprising a storage element; a source line, electrically connected to a first end of the storage element; the memory is configured to change a storage state of the storage element by a first current and a second current, the first current flowing through the storage element and the second current flowing through the source line without flowing through the storage element.Type: GrantFiled: November 20, 2020Date of Patent: January 16, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Baolei Wu, Yulei Wu, Xiaoguang Wang, Erxuan Ping
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Patent number: 11805701Abstract: A memory includes: a substrate, having a plurality of active regions arranged in an array and a plurality of word lines extending in a first direction, the active regions being inclined at a preset angle to the word lines, the active region having at least one access transistor; a plurality of bit lines, extending in a second direction perpendicular to the first direction; magnetic tunnel junctions, one end of the magnetic tunnel junction is electrically connected to one of bit lines and another end of the magnetic tunnel junction is electrically connected to two access transistors, the two access transistors electrically connected to the magnetic tunnel junction being located in two adjacent active regions, respectively.Type: GrantFiled: November 11, 2020Date of Patent: October 31, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Erxuan Ping, Xiaoguang Wang, Baolei Wu, Yulei Wu
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Publication number: 20230217837Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode penetrating the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top surface and sidewalls of the storage structure, wherein the first shielding layer and the second shielding layer combine into one integrated shielding layer; and forming a second electrode which penetrates the shielding layer and electrically connects to the storage structure.Type: ApplicationFiled: March 9, 2021Publication date: July 6, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: YuLei WU, Baolei WU, Xiaoguang WANG, Er-Xuan PING
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Publication number: 20220320422Abstract: A memory includes: a substrate, having a plurality of active regions arranged in an array and a plurality of word lines extending in a first direction, the active regions being inclined at a preset angle to the word lines, the active region having at least one access transistor; a plurality of bit lines, extending in a second direction perpendicular to the first direction; magnetic tunnel junctions, one end of the magnetic tunnel junction is electrically connected to one of bit lines and another end of the magnetic tunnel junction is electrically connected to two access transistors, the two access transistors electrically connected to the magnetic tunnel junction being located in two adjacent active regions, respectively.Type: ApplicationFiled: November 11, 2020Publication date: October 6, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Erxuan PING, Xiaoguang WANG, Baolei WU, Yulei WU
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Publication number: 20220319565Abstract: A memory and a read and write method of memory can prevent the magnetic random-access memory (MRAM) from being easily damaged or degraded by excessive write current during use, and increase memory integration density. The memory includes: a storage unit, comprising a storage element; a source line, electrically connected to a first end of the storage element; the memory is configured to change a storage state of the storage element by a first current and a second current, the first current flowing through the storage element and the second current flowing through the source line without flowing through the storage element.Type: ApplicationFiled: November 20, 2020Publication date: October 6, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Baolei WU, Yulei WU, Xiaoguang WANG, Erxuan PING
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Publication number: 20220208853Abstract: The present application provides a magnetic memory and a reading/writing method thereof. The magnetic memory includes at least one cell layer, the cell layer including: a plurality of paralleled first conductors located in a first plane; a plurality of paralleled second conductors located in a second plane, the first plane being parallel to the second plane, a projection of the second conductor on the first plane intersecting with the first conductor; a plurality of memory elements arranged between the first plane and the second plane, the memory element including a magnetic tunnel junction and a bidirectional gating device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction being connected to the first conductor, the bidirectional gating device being connected to the second conductor, and the bidirectional gating device being configured to be turned on when a threshold voltage and/or a threshold current are/is applied.Type: ApplicationFiled: September 21, 2021Publication date: June 30, 2022Inventors: Baolei WU, Xiaoguang WANG, Yulei WU
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Publication number: 20220208243Abstract: The present application makes public a magnetic memory and a reading/writing method thereof, which magnetic memory comprises at least one cell layer, and the cell layer includes a plurality of parallel second wires that are disposed in a second plane, the first plane being parallel to the second plane, and projections of the second wires onto the first plane intercrossing the first wires; a plurality of storage elements that are disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bi-directional gating components connected in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first wires, the bi-directional gating components being connected to the second wires, and the bi-directional gating components being configured to be conductive upon application of a threshold voltage and/or a threshold current.Type: ApplicationFiled: October 18, 2021Publication date: June 30, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Baolei WU, Xiaoguang WANG, Yulei WU
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Publication number: 20220190236Abstract: Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.Type: ApplicationFiled: July 27, 2021Publication date: June 16, 2022Inventors: Baolei WU, Xiaoguang WANG, Yulei WU
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Publication number: 20220190028Abstract: The present disclosure provides a semiconductor structure and a storage circuit that implements the storage structure of a magnetoresistive random access memory (MRAM) based on a dynamic random access memory (DRAM) fabrication platform.Type: ApplicationFiled: August 3, 2021Publication date: June 16, 2022Inventors: Er-Xuan Ping, Xiaoguang Wang, Baolei Wu, Yulei Wu
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Patent number: 11348972Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate; a first transistor, including a first channel region located in the substrate; a second transistor, including a second channel region located in the substrate, the second channel region having an area different from an area of the first channel region, and the first transistor and the second transistor having a common source or a common drain; and a memory cell, connected to the common source or the common drain.Type: GrantFiled: January 18, 2022Date of Patent: May 31, 2022Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Baolei Wu, Xiaoguang Wang
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Publication number: 20200194498Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
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Patent number: 10629650Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.Type: GrantFiled: August 29, 2018Date of Patent: April 21, 2020Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
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Publication number: 20200075668Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.Type: ApplicationFiled: August 29, 2018Publication date: March 5, 2020Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh