Patents by Inventor Baolin Yang

Baolin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240010271
    Abstract: An EMU bogie and a rubber-tired train are disclosed. The EMU bogie comprises a framework, a first EMU wheelset, a second EMU wheelset and an EMU steering driving device, the framework comprises two side beams opposite to each other and cross beams connected to the two side beams; the first EMU wheelset comprises a first axletree, a first EMU wheel and a second EMU wheel which are arranged at two ends of the first axletree; the second EMU wheelset comprises a second axletree, and a third EMU wheel and a fourth EMU wheel which are arranged at two ends of the second axletree; and the EMU steering driving, device comprises a driving part and a transmission part connected to the driving part, the first EMU wheelset and the second EMU wheelset, and is used for transmitting the steering power to the first EMU wheelset and the second EMU wheelset.
    Type: Application
    Filed: October 14, 2021
    Publication date: January 11, 2024
    Applicant: CRRC NANJING PUZHEN CO., LTD.
    Inventors: Yao XIAO, Xiaoguang MA, Xiangyang TAI, Jun JIANG, Zhijun TANG, Baolin YANG
  • Patent number: 8200467
    Abstract: A method of determining values for a circuit over a cycle includes: specifying first-cycle values for the circuit in a first cycle, the first-cycle values including voltage or current values for the circuit and providing reference cyclic values for characterizing a cyclic behavior of the circuit in the first cycle with a reference cyclic dimension; determining, from the first-cycle values, path-following values for the circuit in a second cycle, wherein the path-following values include transient values for characterizing a transient behavior of the circuit and cyclic-correction values for characterizing the cyclic behavior of the circuit relative to the reference cyclic values from the first cycle, wherein a cyclic-correction dimension of the cyclic-correction values is less than the reference cyclic dimension; and saving at least some values based on the path-following values in the second cycle.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: June 12, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qian Cai, Baolin Yang, Bruce W. McGaughy
  • Patent number: 7783465
    Abstract: A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is a matrix suitable for parallel processing and N is a coupling matrix. M and N are then preconditioned to form M?1Jx=(I+M?1N)x=M?1r and the Jacobian matrix J is solved using an iterative solving method.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: August 24, 2010
    Assignee: Synopsys, Inc.
    Inventor: Baolin Yang
  • Patent number: 7483820
    Abstract: In one embodiment, a method for ranking webpages is provided. The method includes generating a web circuit model having a node representing each webpage. The model is simulated to identify the potential at each node. The webpages can then be ranked according to the potentials of the nodes to which the webpages correspond.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: January 27, 2009
    Assignee: Gemini Design Technology, Inc.
    Inventor: Baolin Yang
  • Patent number: 7428477
    Abstract: A method, computer program product, and apparatus for simulating circuits. The method comprises modeling a circuit with an appropriate system of equations, partitioning a time interval on which the system of equations is defined, producing an interpolating polynomial on the time interval, and applying a two tiered iterative approach to solve the system of equations. The approach begins by decomposing a candidate solution vector into its time domain and frequency domain components. The Fourier transform is applied to the frequency domain components and time domain methods are applied to both the time domain components and the Fourier transformed frequency domain components to generate the solution to the original system of equations. Newton's method can be used in combination with a Krylov iterative subspace solver to perform the two-tiered iteration. The computer program product and the apparatus implement the method of simulating circuits.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 23, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joel R. Phillips, Baolin Yang
  • Patent number: 7373289
    Abstract: Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches. The hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network, where the first and second branches are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. Next, the method determines whether the first and second electrical networks are electrically isomorphic networks. If the first and second electrical networks are determined to be electrically isomorphic networks, the first and second electrical networks are represented with a single electrically isomorphic network. The method further includes simulating the first and second electrical networks using the single electrically isomorphic network.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 13, 2008
    Assignee: Cadence Design Systems, Inc
    Inventors: Bruce W. McGaughy, Wai Chung William Au, Baolin Yang
  • Publication number: 20070244884
    Abstract: In one embodiment, a method for ranking webpages is provided. The method includes generating a web circuit model having a node representing each webpage. The model is simulated to identify the potential at each node. The webpages can then be ranked according to the potentials of the nodes to which the webpages correspond.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 18, 2007
    Inventor: Baolin Yang
  • Patent number: 7269541
    Abstract: A system for supporting multi-rate simulation of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) partitioning the circuit into a plurality of group circuits, each group circuit includes one or more leaf circuits, where each leaf circuit produces a predictable set of output signals with a given set of input signals, 2) storing the group circuits in a scheduled event queue in accordance with priority in time which the group circuits need to be simulated, 3) retrieving from the scheduled event queue a set of group circuits for simulation within a predetermined time period, 4) distributing the set of group circuits into a set of predefined event lists, where each of the predefined event list stores one or more group circuits of a corresponding event type, and 5) simulating the one or more group circuits in each of the predefined event list in accordance with a rate of change of signal conditions of each individual group circuit.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: September 11, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bruce W. McGaughy, Peter Frey, Jun Kong, Baolin Yang
  • Patent number: 7266479
    Abstract: An system and method are disclosed for efficiently approximating analytical circuit device models. A preferred embodiment includes a method for obtaining smooth and accurate approximations of analytical device models, comprising the steps of identifying a first set of measurement units; locating two or more sets of units that neighbor one or more of said measurement units; for each set of the two or more sets of neighbor units, obtaining the union of one or more of said sets of neighbor units and the first set of measurement units; calculating the smoothness of the analytical device model within one or more of said unions; and selecting at least one of said unions within which the analytical device model is the smoothest as the new set of measurement units.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: September 4, 2007
    Assignee: Cadence Designs Systems, Inc.
    Inventors: Baolin Yang, Bruce W. McGaughy
  • Publication number: 20070157135
    Abstract: A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is a matrix suitable for parallel processing and N is a coupling matrix. M and N are then preconditioned to form M?1Jx=(I+M?1N)x=M?1r and the Jacobian matrix J is solved using an iterative solving method.
    Type: Application
    Filed: December 18, 2006
    Publication date: July 5, 2007
    Inventor: Baolin Yang
  • Publication number: 20060111884
    Abstract: Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network, where the first and second branches are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. Next, the method determines whether the first and second electrical networks are electrically isomorphic networks. If the first and second electrical networks are determined to be electrically isomorphic networks, the first and second electrical networks are represented with a single electrically isomorphic network.
    Type: Application
    Filed: November 19, 2004
    Publication date: May 25, 2006
    Applicant: Cadence Design Systems, Inc.
    Inventors: Bruce McGaughy, Wai Chung Au, Baolin Yang
  • Patent number: 7035782
    Abstract: A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: April 25, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Baolin Yang, Joel Phillips
  • Patent number: 7024652
    Abstract: A system for adaptive partitioning of circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first branch and the second branch for simulation, where each leaf circuit is represented by a matrix comprising a set of equations, 2) determining a strength of coupling between two or more leaf circuits of the group in accordance with a set of predetermined electrical coupling criteria, 3) if two or more leaf circuits are deemed be strongly coupled, combining the corresponding matrix of each strongly coupled leaf circuit into a combined matrix, and 4) performing computation for the two or more strongly coupled leaf circuits in accordance with the combined matrix. The system adaptively adjusts the group circuit matrix for computing a group of circuits according to the strength of coupling between the circuits.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: April 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bruce W. McGaughy, Peter Frey, Jun Kong, Baolin Yang
  • Publication number: 20040260523
    Abstract: An system and method are disclosed for efficiently approximating analytical circuit device models. A preferred embodiment includes a method for obtaining smooth and accurate approximations of analytical device models, comprising the steps of identifying a first set of measurement units; locating two or more sets of units that neighbor one or more of said measurement units; for each set of the two or more sets of neighbor units, obtaining the union of one or more of said sets of neighbor units and the first set of measurement units; calculating the smoothness of the analytical device model within one or more of said unions; and selecting at least one of said unions within which the analytical device model is the smoothest as the new set of measurement units.
    Type: Application
    Filed: June 18, 2003
    Publication date: December 23, 2004
    Inventors: Baolin Yang, Bruce McGaughy
  • Publication number: 20030144824
    Abstract: A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.
    Type: Application
    Filed: June 1, 2001
    Publication date: July 31, 2003
    Inventors: Baolin Yang, Joel Phillips