Abstract: The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing SiN/SiON or Si3N4/SiON as a stop layer. The present invention therefore is aimed at reducing underlayer loss and thereby improving the uniformity of the underlayer thickness upon completion of the hole etching process. Concurrently, the over-etch time can be reduced to less than 10% of the time required for Prior Art contact hole etching.

Abstract: A patterned silicon nitride layer formed over a semiconductor integrated circuit wafer having a layer of pad oxide is often used as a mask for subsequent processing steps. Etching of the silicon nitride layer is difficult to control and can create defects in the pad oxide layer which are difficult to detect before the manufacture of the semiconductor integrated circuit wafer is completed. A method is described using potassium hydroxide treatment and scanning electron microscope evaluation of a test wafer for detection of defects at the silicon nitride etching step. Continued processing of defective wafers can be terminated and the silicon nitride etching step can be controlled using this method.