Abstract: A film bulk acoustic resonator and a fabricating method thereof is provided. The fabricating method includes: fabricating a lower electrode on a first surface of an SOI substrate; forming piezoelectric layers on the first surface of the SOI substrate and the lower electrode; forming top electrodes on the piezoelectric layers; processing an air cavity on a second surface of the SOI substrate, wherein the second surface and the first surface are oppositely arranged. The fabricating method simplifies a preparation process of FBAR, a quality of a AlN film crystal grown though the fabrication method is high, an improvement of a device performance is facilitated, and meanwhile a thickness of a top silicon is controlled through a position of a silicon injected oxygen isolation to regulate a frequency of the film bulk acoustic resonator.

Abstract: A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

Abstract: A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

Abstract: The present application discloses a vertical UMOSFET device with a high channel mobility and a preparation method thereof. The vertical UMOSFET device with a high channel mobility includes an epitaxial structure, and a source, a drain and a gate which match the epitaxial structure, where the epitaxial structure includes a first semiconductor, and a second semiconductor and a third semiconductor which are sequentially disposed on the first semiconductor, a groove structure matching the gate is also disposed in the epitaxial structure, and the groove structure continuously extends into the first semiconductor from a first surface of the epitaxial structure; a fourth semiconductor is also disposed at least between an inner wall of the groove structure and the second semiconductor, and the fourth semiconductor is a high resistivity semiconductor.

Abstract: The disclosure provides a gallium oxide film based on sapphire substrate as well as a growth method and an application thereof. The gallium oxide film based on sapphire substrate is prepared by a method below, including: forming more than one ?-(AlxGa1?x)2O3 strain buffering layers on the sapphire substrate by means of pulsed epitaxial growth, wherein 0.99?x?0.01; and forming gallium oxide epitaxial layers on the ?-(AlxGa1?x)2O3 strain buffering layers. The growth method provided can not only avoid the technical difficulty of contradictory epitaxial temperatures of ?-Ga2O3 and ?-Al2O3, but also effectively reduce the defect density of ?-Ga2O3 epitaxial film, thus further improving the crystal quality of the ?-Ga2O3 epitaxial film materials.

Abstract: The present disclosure discloses a ballistic transport semiconductor device based on nano array and a manufacturing method thereof. The ballistic transport semiconductor device based on nano array comprises a conducting substrate, more than one semiconductor nano bump portion is arranged on a first surface of the conducting substrate, a top end of the semiconductor nano bump portion is electrically connected with a first electrode, a second surface of the conducting substrate is electrically connected with a second electrode, the second surface and the first surface are arranged back to back, and the height of the semiconductor nano bump portion is less than or equal to a mean free path of a carrier. The carrier is not influenced by various scattering mechanisms in a transporting procedure by virtue of the existence of ballistic transport characteristics, thereby obtaining a semiconductor device having advantages of lower on resistance, less working power consumption.

Abstract: A film bulk acoustic resonator and a fabricating method thereof is provided. The fabricating method includes: fabricating a lower electrode on a first surface of an SOI substrate; forming piezoelectric layers on the first surface of the SOI substrate and the lower electrode; forming top electrodes on the piezoelectric layers; processing an air cavity on a second surface of the SOI substrate, wherein the second surface and the first surface are oppositely arranged. The fabricating method simplifies a preparation process of FBAR, a quality of a AlN film crystal grown though the fabrication method is high, an improvement of a device performance is facilitated, and meanwhile a thickness of a top silicon is controlled through a position of a silicon injected oxygen isolation to regulate a frequency of the film bulk acoustic resonator.

Abstract: Provided in the present application are a compensator, a control method and device therefor. The compensator comprises: a first inverter, comprising six branch circuits, the branch circuits comprising combined power units and reactors connected in series; the combined power units comprising: first power units and second power units connected in series or second power units connected in series; a first transformer, at least comprising a first side winding and a second side winding, the first side winding being connected to an alternating current-side interface of the first inverter, the second side winding being connected in series to a circuit of an alternating current system; the second side winding being connected in parallel on either end to a switch; and the switch, connected in parallel to the first transformer and then connected to the circuit of the alternating current system.

Abstract: A method and apparatus for suppressing the impact of a compensator on line distance protection is provided, wherein the method comprises: obtaining a first current of a line connected to a compensator or series converters in the compensator, and a first voltage of a bus connected to the compensator or the line connected to the compensator; exiting the series converters and series transformers if the first current is greater than a preset current threshold and a duration is greater than a first preset time threshold; exiting the series converters and the series transformers if the first voltage is less than or equal to a preset voltage threshold and duration is greater than a second preset time threshold set the output voltage of the series converters to zero, and if a second current of an element corresponding to the first current meets conditions which the first current needs to meet; and otherwise, canceling the setting of the output voltage of the series converters to zero and obtaining a first current if

Abstract: A new RF/microwave energy harvesting device based on spintronics is provided. The device comprises at least one RF/microwave energy conversion element comprising a first magnetic layer connected to a RF/microwave signal receiving element; a non-magnetic space layer; and an energy conversion layer accumulating positive and negative charges at both of upper and lower ends of the RF/microwave energy conversion element to implement a conversion of a RF/microwave energy into a direct voltage signal. Compared with the prior art, the device has advantages such as a simple structure, a small size, a wide operating frequency and the like.

Abstract: The present disclosure discloses a ballistic transport semiconductor device based on nano array and a manufacturing method thereof. The ballistic transport semiconductor device based on nano array comprises a conducting substrate, more than one semiconductor nano bump portion is arranged on a first surface of the conducting substrate, a top end of the semiconductor nano bump portion is electrically connected with a first electrode, a second surface of the conducting substrate is electrically connected with a second electrode, the second surface and the first surface are arranged back to back, and the height of the semiconductor nano bump portion is less than or equal to a mean free path of a carrier. The carrier is not influenced by various scattering mechanisms in a transporting procedure by virtue of the existence of ballistic transport characteristics, thereby obtaining a semiconductor device having advantages of lower on resistance, less working power consumption.

Abstract: A method and apparatus for suppressing the impact of a compensator on line distance protection is provided, wherein the method comprises: obtaining a first current of a line connected to a compensator or series converters in the compensator, and a first voltage of a bus connected to the compensator or the line connected to the compensator; exiting the series converters and series transformers if the first current is greater than a preset current threshold and a duration is greater than a first preset time threshold; exiting the series converters and the series transformers if the first voltage is less than or equal to a preset voltage threshold and duration is greater than a second preset time threshold set the output voltage of the series converters to zero, and if a second current of an element corresponding to the first current meets conditions which the first current needs to meet; and otherwise, canceling the setting of the output voltage of the series converters to zero and obtaining a first current if

Abstract: The present invention provides a terahertz source chip, a source device, a source assembly and manufacturing methods thereof. The source chip comprises: a two-dimensional electron gas mesa; an electrode formed on the two-dimensional electron gas mesa for exciting a plasma wave; a terahertz resonant cavity formed below the two-dimensional electron gas mesa, the terahertz resonant cavity having a total reflector on a bottom surface thereof; and a grating formed on the two-dimensional electron gas mesa for coupling a plasma wave pattern with a cavity mode of the terahertz resonant cavity to generate terahertz radiation. In the present invention, a plasmon polariton is formed by strongly coupling the cavity mode of the terahertz resonant cavity with the plasma wave mode in the two-dimensional electron gas below the grating, and the terahertz wave emission is realized by electrical excitation of the plasmon polariton.

Abstract: A group III nitride high electron mobility transistor (HEMT) device comprises a source electrode (112), a drain electrode (111), a main gate (116), a top gate (118), an insulating dielectric layer (117) and a heterostructure, wherein the source electrode (112) and the drain electrode (111) are electrically connected via two-dimensional electron gas (2DEG) formed in the heterostructure; the heterostructure comprises a first semiconductor (113) and a second semiconductor (114); the first semiconductor (113) is disposed between the source electrode (112) and drain electrode (111); the second semiconductor (114) is formed on the surface of the first semiconductor (113) and is provided with a band gap wider than the first semiconductor (113); the main gate (116) is disposed at the side of the surface of the second semiconductor (114) adjacent to the source electrode (112), and is in Schottky contact with the second semiconductor (114); the dielectric layer (117) is disposed on the surfaces of the second semiconduc

Abstract: A group III nitride high electron mobility transistor (HEMT) device comprises a source electrode (112), a drain electrode (111), a main gate (116), a top gate (118), an insulating dielectric layer (117) and a heterostructure, wherein the source electrode (112) and the drain electrode (111) are electrically connected via two-dimensional electron gas (2DEG) formed in the heterostructure; the heterostructure comprises a first semiconductor (113) and a second semiconductor (114); the first semiconductor (113) is disposed between the source electrode (112) and drain electrode (111); the second semiconductor (114) is formed on the surface of the first semiconductor (113) and is provided with a band gap wider than the first semiconductor (113); the main gate (116) is disposed at the side of the surface of the second semiconductor (114) adjacent to the source electrode (112), and is in Schottky contact with the second semiconductor (114); the dielectric layer (117) is disposed on the surfaces of the second semiconduc